Mit Patel

Software Engineer

Bengaluru, Karnataka, India7 yrs 7 mos experience

Highly Stable

Key Highlights

Experienced in Functional Verification and RTL Design.
Proficient in multiple programming languages including Java and SystemVerilog.
Strong background in ASIC and SoC design methodologies.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Functional Verification and ASIC methodologies.

Contact

Skills

Core Skills

Functional VerificationJava

Other Skills

VerdiVerilogJavaScriptEthernet subsystemDebuggingNetworking BasicRTL DesignApplication-Specific Integrated Circuits (ASIC)System on a Chip (SoC)RTL VerificationUniversal Verification Methodology (UVM)SystemVerilogGigabit EthernetPCIeAXI

About

Work to become not to acquire!

Experience

7 yrs 7 mos

Total Experience

2 yrs 11 mos

Average Tenure

1 yr 8 mos

Current Experience

Microsoft

Verification Engineer II

Oct 2024 – Present · 1 yr 8 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

2 roles

IP Verification Engineer

Jul 2020 – Oct 2024 · 4 yrs 3 mos · Bengaluru, Karnataka, India

Functional VerificationVerdi

Graduate Technical Intern

Jun 2019 – May 2020 · 11 mos · Banglore

Functional VerificationVerilog

Cybage software

Java Developer

Nov 2016 – Jul 2018 · 1 yr 8 mos · Gandhi Nagar, Gujarat, India

JavaJavaScript

Education

Institute of Technology, Nirma University

Master of Technology - MTech — VLSI - Design

Jan 2018 – Jan 2019

L.D. College of Engineering

BE - Bachelor of Engineering

Jan 2012 – Jan 2016

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