Tulasiram P.S — Software Engineer

Experienced professional with 11 years of experience in Verification. A Master Graduate from College of Engineering Guindy. Have demonstrated quick learning, good analytical ability, creativity, and dedication. Brief Summary of Experience: - Constrained-Random and Coverage Driven Verification. - Building Functional Verification Environment. - Develop Coverage Plan and Implement Functional coverage. - Development of test plans & functional test cases. - Generated focused and random test cases and debugging failure cases. - Code Coverage Analysis. Specialties: - Standard Protocols: NVMe, PCIe(NVMe Oriented), DDR5, AXI, SPI and I2C - Verification Languages: SystemVerilog - Verification Methodologies: UVM - Simulation & Debug Tools: Mentor (Questa) , Cadence (IUS), Synopsys(Verdi) - Other Skills: LINUX, C/C++ (Basics). - Repositories: CVS, Perforce,Git

Stackforce AI infers this person is a Verification Engineer specializing in semiconductor technologies.

Location: Bengaluru, Karnataka, India

Experience: 11 yrs