Aug 2022 – Dec 2022 · 4 mos · Austin, Texas, United States

Aug 2021 – May 2023 · 1 yr 9 mos · Atlanta, Georgia, United States

• GPA: 4.0/4.0
• Awarded a Master's degree in ECE with a focused specialization in VLSI Systems and Computer Architecture.
• Coursework & Internships:
• Spring 2023:
• Reliability and Security in Computer Architecture
• Machine Learning
• Technology Entrepreneurship
• Fall 2023:
• Co-op Internship @ Apple
• Summer 2022:
• Summer Internship @ Nvidia
• Spring 2022:
• Physical Design Automation of VLSI Systems
• Advanced Operating Systems
• Parallel programming for FPGAs
• Interconnection Networks
• Fall 2021:
• Advanced VLSI Design
• Advanced Computer Architecture
• Digital Systems Test
• Advanced Programming Techniques

Dec 2017 – Jul 2021 · 3 yrs 7 mos · Greater Bengaluru Area

• Areas of Proficiency:
• 3+ years of experience in Physical Design Implementation (Synthesis, floorplanning, CTS, Routing) with STA convergence and Reliability Verification of complex networking IP blocks based on Intel’s 10nm and TSMC’s 7nm process nodes. Familiar with backend layout, LEC sign-off flows and the Synopsys EDA tool stack.
• Shared Slice Controller IP:
• Responsible for design synthesis, placement, convergence and sign-off of a complicated controller block with multiple macros and high criss-cross routing density.
• Engaged with RTL owners to get a deep understanding of the block’s architecture to achieve an optimal floorplan and accelerate convergence. Converged the design to tape-in within stringent timelines.
• Worked with floorplan owners to mitigate challenges arising due to multi-instantiated blocks in the IP floorplan.
• Handled subsystem timing analysis and generated ECOs for interface and partition level STA sign-off.
• Scalable HPC Coherent Mesh Network IP:
• Design owner for Synthesis and PnR execution of multiple high-speed design blocks in a mesh network.
• Finalized custom place-and-route recipes to optimize critical data paths and reduce clock skew to achieve timing convergence and improve overall design QoR.
• Reliability Verification owner for all partitions in an SoC IP. Performed Power Grid weakness checks, SignalEM and Dynamic/Static IR drop analysis with Redhawk for all partitions in an SoC IP.
• Intel 10nm wireless base station SoC:
• Responsible for PnR execution of multiple blocks including complex designs from the Remote Direct Memory Access (RDMA) sub-IP.
• Automated generation of multiple ECO’s to fix timing, MaxTrans and MaxCap violations for signoff convergence.
• Fixed critical Pattern must-join requirements through tool-based automation and DRC aware tail end fixes. Worked on Full-chip layout integration, fixed physical DRC and density violations for sub-IPs.

Jul 2016 – Dec 2017 · 1 yr 5 mos · Greater Bengaluru Area

• Experienced in high-speed PCB design and validation of PC Client Platforms. Designed various storage (SATA, M.2, UFS, eMMC) and display (eDP 1.3, HDMI 1.4) interfaces.
• Contributed to various platform and silicon power-on activities. Performed electrical validation of various on-board interfaces.

Jan 2016 – Jun 2016 · 5 mos · Greater Bengaluru Area

• Investigated high-speed interconnect designs based on Single Wire Communication technology.
• Simulated and iteratively modified geometries of PCB level structures using the Ansys High Frequency Structure Simulator (HFSS) tool.
• Demonstrated the concept of ‘Ambient passive sensing’ through a simulated prototype of a passive audio sensor.

May 2015 – Jul 2015 · 2 mos · Mumbai Metropolitan Region

• Programmed Schneider and Selec PLCs at the Accelerator and Pulse Power Division of BARC to implement ladder logic programs required to generate and measure the frequency of trigger pulses needed for a Klystron Modulator.

May 2014 – Jul 2014 · 2 mos · Mumbai Metropolitan Region

• Analyzed the existing planning process for a GSM Network. Designed a plan for a GSM Radio Network.