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Nagabhushanam Vuddagiri

Co-Founder

Bengaluru, Karnataka, India10 yrs 8 mos experience

Key Highlights

  • Expert in Physical Design and Static Timing Analysis.
  • Led teams in advanced technology nodes like 4nm and 3nm.
  • Extensive experience across major semiconductor companies.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Static Timing Analysis.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

FloorplanningLECvclpVLSILVSXilinxFunctional VerificationDRCPower AnalysisSemiconductorsTCLPlace & RoutePrimetimeTiming ClosurePerl

About

Working for AMD as a contractor Previously worked for Google as a contractor and handled group of critical sub-systems along with Junior engineers team. Worked for Intel bangalore and Malaysia locations remotely and handled sub system level designs for PNR implementation and STA. Worked for Microchip Technologies through UST Global as a Service provider for Penang location, Malaysia. Worked with Synapse for last 3 years as technical lead and worked on latest technology node in my recent project. Worked with SoCtronics Technologies Private Limited, Hyderabad for about 3.4 Years as Physical Design Engineer. Areas of work includes Physical implementation of Million instance blocks from Netlist to GDSII . Hands on experience in PnR flow for block level as well as full-chip, STA and Physical Verification. Feasibility studies on latest PCIE architecture; deciding chip area based on MFU etc.

Experience

10 yrs 8 mos
Total Experience
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Average Tenure
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Current Experience

Google

Consultant

Jan 2022 – Jul 2023 · 1 yr 6 mos · Bengaluru, Karnataka, India · Hybrid

  • Handled 2 sub systems along with a team of Engineers and executed from RTL to GDS for lower technology nodes 4nm and 3 nm.
Static Timing AnalysisLECPhysical DesignvclpFloorplanning

Intel corporation

Consultant

Sep 2019 – Sep 2021 · 2 yrs

  • Worked for different teams and on latest flows for PNR implementation
Static Timing AnalysisLECPhysical DesignvclpFloorplanning

Fabic design solutions pvt ltd

Co-Founder

Jul 2019 – Present · 6 yrs 11 mos · Bengaluru Area, India

FloorplanningPhysical Design

Ust global

Senior Techincal Analyst

Apr 2018 – May 2019 · 1 yr 1 mo · Penang, Malaysia

  • Worked for Microchip Technologies as Service provider
Static Timing AnalysisLECPhysical DesignvclpFloorplanning

Synapse design inc.

Technical Lead

May 2015 – Mar 2018 · 2 yrs 10 mos · Bengaluru Area, India

  • From more than a year, I have worked in ODC as a team lead and on 7nm technology node.
  • I was Working with Mediatek Bangalore as a contract Engineer.
  • Earlier worked with Texas Instruments as a contract engineer. Handling fullchip activities like physical verification flow for the testchips and power grid implementation including bump placement and routing.
Static Timing AnalysisLECPhysical DesignvclpFloorplanning

Soctronics

Physical Design Engineer

Jan 2012 – Apr 2015 · 3 yrs 3 mos · Hyderabad Area, India

  • My responsibilities includes block level PNR closure along with STA and PV signoff things
Static Timing AnalysisLECPhysical DesignvclpFloorplanning

Education

J N T University

B.Tech — Electronics and Communication

Jan 2007 – Jan 2010

S B T E T

Diploma — ECE

Jan 2004 – Jan 2007

ZPH School

SSC — Schooling

Jan 1996 – Jan 2000

padmasri convent , annavaram

schooling

Jan 1990 – Jan 1995