Rahul Jha

Software Engineer

Noida, Uttar Pradesh, India1 yr 10 mos experience

Key Highlights

Expert in compiler and runtime optimizations.
Proven track record in performance engineering.
Strong background in low-latency systems.

Stackforce AI infers this person is a Semiconductor Performance Engineer with expertise in compiler optimizations and systems architecture.

Contact

rahujha04@gmail.com LinkedIn

Skills

Core Skills

Compiler OptimizationPerformance Engineering

Other Skills

STLMultithreadingMemory ManagementPerformance ProfilingLow-level DebuggingCache ManagementSystems DesignLow LatencyHigh-Frequency TradingLow Latency InfrastructureProfiling & DebuggingSimulation SystemsCompiler DesignObject-Oriented DesignConcurrency

About

I specialize in building and optimizing high-performance software systems where latency, scalability, and efficiency matter. Currently, I work as a Software Engineer at Siemens EDA on the Questa Optimization Team, developing compiler and runtime optimizations for the Questa HDL simulator. My work focuses on improving simulation scalability, reducing scheduling overhead, optimizing memory usage, and accelerating critical execution paths used in production verification workloads for companies including NVIDIA, Intel, Microsoft, Qualcomm, and other leading semiconductor firms. Core Areas of Interest: • Performance Engineering & Runtime Optimization • Low-Latency Systems & Concurrency • Compiler Optimizations & Execution Pipelines • Multithreading, Synchronization & Memory Management • Systems Architecture & Scalable Infrastructure I also enjoy building systems-focused projects including: • Exchange-style Order Matching Engines • Multi-Level Cache Architectures • Thread Pools & Concurrent Execution Infrastructure Competitive Programming: • LeetCode Knight (Max Rating: 1985) • Google Kick Start Global Rank 870 • Codeforces Specialist Currently exploring distributed systems, scalable backend infrastructure, and advanced systems design. Open to opportunities in systems engineering, infrastructure, low-latency backend, compiler/runtime, and performance-focused software development. Email: rahujha04@gmail.com

Experience

1 yr 10 mos

Total Experience

1 yr 10 mos

Average Tenure

1 yr 10 mos

Current Experience

Siemens eda (siemens digital industries software)

3 roles

Senior Member of Technical Staff

Promoted

Jan 2026 – Present · 5 mos · Noida, Uttar Pradesh, India · On-site

Developed compiler/runtime optimizations for the Questa HDL simulator, improving simulation scalability and reducing scheduling overhead by up to 25% on large production workloads.
Accelerated GPU verification workloads for a global leader in AI computing by implementing radix-8 Fast Exponentiation, optimizing critical hot paths through bitwise decomposition and algebraic power reuse.
Extended loop coalescing, vectorization, and reduction-recognition optimizations for complex HDL patterns, improving simulation efficiency by 18% across FPGA-scale designs for Tier-1 cloud and mobile SoC providers.
Reduced vopt memory usage by 1.2 GB (16%) by refactoring optimization flows and eliminating unnecessary compiler data-structure allocations.
Lowered ASM footprint by 15% through legality-aware optimizations for multi-driver and scheduling-sensitive scenarios while strictly preserving Verilog semantics.
Diagnosed and resolved long-standing simulator correctness issues involving feedback loops, race conditions, and elaboration-error propagation.

STLMultithreadingCompiler OptimizationPerformance Engineering

Member of Technical Staff

Jul 2024 – Dec 2025 · 1 yr 5 mos · Noida, Uttar Pradesh, India · On-site

Software Engineering Intern

Jan 2024 – Jun 2024 · 5 mos · Noida, Uttar Pradesh, India · On-site

Engineered optimization heuristics that eliminated simulation regressions causing up to 1.41× slowdown on large production workloads for a leading x86 semiconductor manufacturer.
Performed low-level debugging and performance profiling using GDB and Oracle Profiler to identify runtime bottlenecks and memory hotspots in production-scale compiler infrastructure.
Contributed to compiler/runtime infrastructure involving scheduling semantics, elaboration flows, dependency analysis, and performance-sensitive execution pipelines.