Siddhant Y.

Software Engineer

Bengaluru, Karnataka, India7 yrs 9 mos experience

Key Highlights

Expert in advanced semiconductor flow deployments.
Proven track record in reliability and power optimization.
Hands-on experience with leading foundries like TSMC and Intel.

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on reliability and power optimization.

Contact

Skills

Core Skills

ReliabilityPower Optimization

Other Skills

AutomationPDNRedhawkRedhawkScESDElectrostatic Discharge (ESD)power delivery networkverilogDigital ElectronicsCApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)Integrated Circuits (IC)SemiconductorsAnalog Circuit Design

About

As a Staff Engineer at Synopsys Inc, I contribute to advanced flow deployments, including SigmaAV, SigmaPD, and mixed tool flows like IRSTA and IRECO. My role involves supporting Tier 1 and Tier 2 accounts, delivering critical tape-out support, and addressing reliability, compute, and disk challenges. Additionally, I specialize in 2.5D (Interposer) and 3D flows and thermal integrity solutions for leading foundries like TSMC, Samsung, and Intel. With a Bachelor's degree in Electrical and Electronics Engineering from UPTU, I have cultivated a strong foundation in reliability, power optimization, and automation. My career includes hands-on expertise in IC layout design, physical verification.I am driven to provide innovative solutions and ensure robust performance across lower nodes and advanced design processes.

Experience

7 yrs 9 mos

Total Experience

Average Tenure

Current Experience

Synopsys inc

Staff Engineer

Oct 2025 – Present · 8 mos · Hybrid

ReliabilityPower OptimizationAutomationPDNRedhawkRedhawkSc+49

Ansys

Application Engineer

Oct 2022 – Present · 3 yrs 8 mos · Bengaluru, Karnataka, India

Specilization in Redhawk SC , Redhawk , Path Finder and PathFinderSC while supporting multiple Tier1 and Tier2 accounts individually
Deployment of advanced flows :
SigmaAV and SigmaPD
Mixed Tools flows:
IRSTA AND IRECO
Deployment of 2.5D(Interposer) and 3D flows for TIER1 Customers
Deployment of Thermal Integrity flows for various foundries:TSMC,Samsung and Intel.
Involved in critical evaluations and QoR analysis
Lead multiple post silicon debugs for TIER1 accounts
Resolved multiple compute and disk issues for Tier1 and Tier2 accounts
Resolved multiple over-designing issues for Tier1 and Tier2 customers
Provided critical tape out support.

PDNpower delivery networkRedhawkRedhawkScESDElectrostatic Discharge (ESD)+2

Amd

Senior Mask Desiger( AMD acquires Xilinx)

Feb 2022 – Oct 2022 · 8 mos · Hyderabad, Telangana, India

Physical DesignReliabilityPower OptimizationAutomationroutingPhysical Verification

Xilinx

2 roles

IC Layout Design Engineer 2

Dec 2021 – Oct 2022 · 10 mos

IC layout Design Engineer

May 2020 – Dec 2021 · 1 yr 7 mos

Cadence design systems

Solution Engineer/AUTOMATION (PVS)

Nov 2019 – May 2020 · 6 mos · Bengaluru Area, India

I worked for the SIGNOFF PVS tool team inside Càdence. Automating the validation flows of DRC/LVS/DFM and correcting and writing DFM and LVS rule decks.