V

Vishakh Venugopal

Software Engineer

Bangalore, Karnataka, India7 yrs experience

Key Highlights

  • 6 years of VLSI industry experience
  • Expertise in SoC verification and automation
  • Advanced Python programming for scalable solutions
Stackforce AI infers this person is a Semiconductor Verification Engineer with strong automation skills.

Contact

Skills

Core Skills

DebuggingVerificationAutomation

Other Skills

DFXJoint Test Action Group (JTAG)VerdiPythonC++Data StructuresJTAGMBISTPerlShell ScriptingSystemVerilogData AnalysisAlgorithmic TradingTest AutomationTableau

About

A passionate VLSI professional with 6 years of industry experience, specializing in the verification and validation of complex SoC designs. I hold a Master’s degree in VLSI Design from NITK Surathkal, where I built a strong foundation in digital design and verification, complemented by a year-long internship at Intel as a Graduate Technical Intern. Currently, I work at Qualcomm, where I focus on post-silicon debug support for Snapdragon CPUs, scandump collection and decoding, automation of debug flows and development of debug infrastructure. Over the past 5 years in AMD, I have gained strong expertise in the verification of non-scan features such as JTAG, clocking, and MBIST, enabling me to contribute to the robustness and reliability of advanced SoC architectures. I am deeply motivated by solving complex verification challenges and accelerating debug workflows through automation. As an advanced-level Python programmer, I leverage object-oriented design principles to develop efficient and scalable solutions for diverse problems. I am also proficient with industry-standard debug tools like Verdi, which strengthen my ability to analyze, isolate, and resolve issues effectively.

Experience

7 yrs
Total Experience
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Average Tenure
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Current Experience

Qualcomm

Senior Lead Engineer

Jun 2025Present · 1 yr · Bengaluru · On-site

  • Working on CPU debug infrastructure development for Snapdragon SoCs
  • Responsible for scandump validation, analysis, and decoding across all CPU targets
  • Supporting internal teams with scandump collection, interpretation, and debug assistance. Cross team interactions with DFT, DV and CAD.
DFXJoint Test Action Group (JTAG)DebuggingVerdiPythonVerification

Amd

2 roles

Sr. Silicon Design Engineer

Promoted

Sep 2022Jun 2025 · 2 yrs 9 mos

  • Owned SoC-level MBIST verification for multiple server-class SoCs, ensuring robust test coverage and silicon readiness
  • Experience with JTAG, clocking architectures, and IEEE 1687 (IJTAG) features and validation
  • Proficient in Perl, Python, CSH, and C++ for automation, scripting, and verification flow optimization
  • Supported silicon bring-up, ATE pattern delivery, and post-silicon debug activities
  • Developed automation to optimize test patterns and reduce bring-up cycle time
  • Collaborated with cross-functional, multi-site global teams
C++Data StructuresJTAGMBISTPerlPython+2

Design Engineer 2

Jun 2019Sep 2022 · 3 yrs 3 mos

  • A part of the AMD Server SOC DFT verifcation team and successfully contributed to development of 3 generations of SOCs.

Intel corporation

Intern

Jun 2018May 2019 · 11 mos · Bangalore

  • Worked in the Platform Development team, implementing the DFT MBIST architecture for 14nm and 22nm memory IPs, with focus on automation of the flows using Perl and shell scripts.
PerlShell Scripting

Education

National Institute of Technology Karnataka

Master of Technology - MTech — VLSI Design

Jan 2017Jan 2019

College of Engineering Trivandrum

Bachelor of Technology - BTech

Jan 2012Jan 2016

Kristu Jyoti Higher Secondary School, Changanassery

12th Standard — Computer Science

Jan 1999Jan 2012

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