AK Sinha

Software Engineer

Bengaluru, Karnataka, India4 yrs 2 mos experience
AI EnabledAI ML Practitioner

Key Highlights

  • AMD Spotlight Award for FlexML Graph Compiler contributions
  • AlphaICs Excellence Award for graph compiler development
  • Expert in edge AI and compiler optimization strategies
Stackforce AI infers this person is a specialist in AI hardware and compiler optimization for edge applications.

Contact

Skills

Core Skills

Edge AiCompilers

Other Skills

Field-Programmable Gate Arrays (FPGA)CIRCTMLIRNatural Language Processing (NLP)LLVMyosysXilinx VivadokernelsConvolutional Neural Networks (CNN)GNU DebuggerLong Short-term Memory (LSTM)ONNXLLDBDeep LearningLarge Language Models (LLM)

About

I am an experienced ML systems engineer with over 5 years of expertise in delivering production-grade solutions in edge AI and accelerator-driven environments. My passion lies in designing end-to- end model execution frameworks that facilitate the seamless deployment of deep learning workloads on resource-constrained hardware. I specialize in developing compiler-centric optimization strategies that effectively bridge high-level ML abstractions with efficient low-level execution, ensuring optimal performance across various platforms. Throughout my career, I have demonstrated a strong ability to design and optimize production-grade inference engines for edge ML accelerators. My work has involved leveraging advanced graph compiler techniques to convert ONNX models into highly efficient C++ implementations. I am also knowledgeable in hardware-aware model transformation techniques, which ensure the optimal utilization of compute, memory, and dataflow architectures. My commitment to performance engineering has driven significant latency reduction and throughput improvements for real-time inference applications. 🏆 Key Achievements: 👉🏼 Honored with the AMD Spotlight Award (2025) for impactful contributions to the FlexML Graph Compiler and advancing the AI Engine-ML architecture for Ryzen AI NPUs and Versal adaptive SoCs. 👉🏼 Recognized with the AlphaICs Excellence Award (2022) for outstanding performance in graph compiler development, ML kernel optimization, and building scalable CI/CD infrastructure for the RAP™ architecture.

Experience

4 yrs 2 mos
Total Experience
1 yr 11 mos
Average Tenure
3 mos
Current Experience

Stealth ai

SDE III

Mar 2026Present · 3 mos · Switzerland · Remote

  • In my current role, I engineer MLIR-driven compilation workflows that leverage CIRCT to enable RTL generation and intermediate representation transformation targeting physical hardware. I validate hardware implementations using Verilator and Arcilator to achieve cycle-accurate simulation and functional correctness. Additionally, I strengthen FPGA verification pipelines by integrating high-level IR stages with hardware execution layers, ensuring consistency across abstraction levels.
  • 🏆 Achievements: I have successfully enhanced the hardware compilation process, leading to improved efficiency and accuracy in RTL generation. My contributions have significantly advanced the verification processes, ensuring high-quality hardware implementations.
Field-Programmable Gate Arrays (FPGA)CIRCTEdge AICompilers

Amd

SDE II

Feb 2023Mar 2025 · 2 yrs 1 mo · Hyderabad · On-site

  • In this role, I played a key part in enhancing AMD’s FlexML Graph Compiler, enabling efficient execution on the AI Engine-ML architecture for Ryzen AI NPUs and Versal adaptive SoCs. I diagnosed combinatorial complexity across 50+ DAG APIs and implemented a unified templated parameter-generation framework, which reduced redundancy and improved maintainability. I also re- architected legacy code generation modules into modular OOP-driven compiler passes.
  • 🏆 Achievements:
  • My efforts led to significant improvements in the FlexML Graph Compiler & performance and maintainability, directly impacting the efficiency of AI workloads on AMD hardware.
MLIRNatural Language Processing (NLP)CompilersEdge AI

Alphaics

SDE I -> SDE II

Mar 2021Jan 2023 · 1 yr 10 mos · Bengaluru · On-site

  • I contributed to the development of AlphaICs’ AlphaNE Graph Compiler and hand- optimized kernel implementations for the RAP™ (Real AI Processor). I constructed a complete graph lowering pipeline that transformed ONNX models into MLIR IRs and optimized C++ code using RAP intrinsics. My work included designing subgraph partitioning, node fusion, and execution chaining mechanisms to enhance data locality and reduce memory round-trips.
  • 🏆 Achievements:
  • I successfully optimized the graph compiler and kernel implementations, resulting in improved performance and energy efficiency for edge AI inference applications.
MLIRNatural Language Processing (NLP)CompilersEdge AI

Education

Jadavpur University, Kolkata

Bachelor of Engineering — Computer Science

Jun 2017Aug 2021

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