Yajuvendra Dhavalikar — Product Manager
ASIC Verification Engineer Specialties:Functional Verification of IPs using UVM/OVM/SystemVerilog NLP(UPF based) Languages: SystemVerilog, UVM, OVM, Verilog, VHDL, C/C++ EDA Tools: Synopsys VCS and Verdi, Cadence SoC Encounter, Virtuosoe, DVE Xilinx ISE, ModelSim, QuestaSim
Stackforce AI infers this person is a highly skilled ASIC Verification Engineer with expertise in VLSI and EDA tools.
Location: Bengaluru, Karnataka, India
Experience: 14 yrs 5 mos
Career Highlights
- Expert in ASIC Verification with UVM/SystemVerilog.
- Proficient in multiple EDA tools including Synopsys and Cadence.
- Strong background in Functional Verification of IPs.
Work Experience
Intel Corporation
Pre-Silicon Validation Engineer (4 yrs 2 mos)
Consultant (1 yr 9 mos)
Cypress Semiconductor Corporation
Consultant (11 mos)
Rockwell Automation
Consultant (2 yrs)
Broadcom
Consultant (1 yr 5 mos)
Qualcomm
Consultant (10 mos)
Wafer Space
Staff Design Engineer (7 yrs 7 mos)
AMD
Consultant (2 yrs 6 mos)
SmartPlay Technologies
Associate Engineer (2 yrs 8 mos)
Education
M.tech at National Institute of Technology Karnataka
B.E. at RIEIT
