Prakhar Srivastava

Software Engineer

Bengaluru, Karnataka, India7 yrs 7 mos experience

Highly Stable

Key Highlights

7+ years of experience in design verification.
Delivered first-pass silicon success across multiple projects.
Expert in low-power verification and automation.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in low-power SoCs and HDMI standards.

Contact

Skills

Core Skills

Ddr SdramVerificationDebuggingAssertionsLow-power SocPost-silicon ValidationHdmi VerificationAutomation

Other Skills

Amba chiAmba axiCoverage closureCommunicationCXPROPTest planningGPIOPower estimationFunctional validationAPBVerilogVMMRegression coverageUVM

About

I am a Design Verification Engineer with 7+ years of experience delivering first-pass silicon success across DDR, HDMI, eARC, and low-power SoCs. Currently at Cadence Design Systems, I specialize in UVM, SystemVerilog, assertions (SVA), coverage closure, and low-power verification (UPF). At NXP, I drove ultra-low power SoC verification and post-silicon validation, directly improving power efficiency and enabling tape-out success. At Synopsys, I led verification for HDMI21RX and eARC TX, achieving zero major escapes and introducing automation that cut debug time by 30%. What sets me apart is end-to-end project ownership—from test planning and regression management to silicon bring-up and validation. I thrive at the intersection of technical depth and problem-solving, ensuring designs are robust, efficient, and future-ready.

Experience

7 yrs 7 mos

Total Experience

1 yr 6 mos

Average Tenure

1 yr 5 mos

Current Experience

Cadence

Lead Design Engineer

Jan 2025 – Present · 1 yr 5 mos · Noida, Uttar Pradesh, India · On-site

DDR Memory Controller (Project 1)
Migrated legacy testbench to align with latest VIPs.
Ran regressions, debugged AXI interface issues, and worked with design teams to drive fixes.
Ensured compatibility with evolving protocol models while maintaining regression quality.
DDR Memory Controller (Project 2)
Added assertions for new I/O ports, ensuring design intent correctness.
Expanded coverage with additional coverpoints for new parameters/signals and clock frequencies.
Reported missing design documentation to design teams, strengthening spec clarity.
Key Achievements:
✅ Improved debug efficiency, enabling faster closure of AXI interface issues.
✅ Recognized for elevating verification maturity within a short span.

Amba chiAmba axiDDR SDRAMVerification

Nxp semiconductors

Lead Engineer

Jan 2023 – Jan 2025 · 2 yrs · Noida, Uttar Pradesh, India · Hybrid

Ultra-Low Power SoC (Initial Phase)
Performed XPROP cleanup and expanded regressions to improve design robustness.
Authored directed/random testcases to boost coverage and ensure functional completeness.
Debugged RTL/simulation mismatches, resolving high-priority corner-case bugs.
Partnered with power estimation teams to provide clean simulation models and analyze leakage/switching activity.
Ultra-Low Power SoC (Advanced Phase)
Designed comprehensive register/IP testcases (CRC, PORT, RGPIO), focusing on low-power flows.
Verified wakeup tests from sleep mode using GPIO pins to ensure ultra-low power operation.
Automated power estimation regression runs and resolved memory-loading bottlenecks.
Managed testbench releases, regression cleanups, and coverage closure.
Post-Silicon Validation
Conducted functional validation of GPIO, PORT, and CRC IPs on silicon.
Debugged register access issues on IAR Embedded Workbench, enabling silicon stability.
Collaborated with validation engineers to bridge pre-silicon/post-silicon debug and accelerate bring-up.
Key Achievements:
✅ Delivered first-pass silicon success, saving re-spin cost and timeline.
✅ Owned low-power verification flows, directly contributing to product power efficiency.
✅ Introduced automated regression cleanup/reporting, improving turnaround.
✅ Acted as a bridge between design, verification, and validation, accelerating debug closure.

CommunicationCLow-power SoCVerification

Synopsys inc

2 roles

ASIC Digital Design Engineer 2

Promoted

Nov 2021 – Jan 2023 · 1 yr 2 mos · Noida, Uttar Pradesh, India

HDMI21RX (HDMI 1.4, 2.0 & 2.1 modes)
Owned complete verification strategy from planning to silicon success.
Designed and debugged testbenches/checkers in Verilog & VMM, covering FRL and TMDS modes.
Built and maintained RAL model for register-level verification, accelerating testcase creation.
Executed GLS & GTECH verification, PCS-level validation, and link training/error recovery tests.
Optimized firmware adaptation checker, improving calibration accuracy.
Integrated SRAM support into VMM TB; provided RTL sim support to COSIM team.
Drove UPF-based power verification, validating low-power intent and shutdown/wakeup flows.
eARC TX (Enhanced Audio Return Channel Transmitter)
Verified Differential, Common, ARC Common, and Single modes for spec compliance.
Developed register access tests using APB/CR interfaces.
Authored protocol-specific testcases and enhanced regression coverage.
Conducted GLS/GTECH verification, added new checkers, and debugged complex regressions.
Optimized regression scripts, reducing runtime and debug turnaround.
Key Achievements:
✅ Delivered first-pass silicon success for HDMI21RX & eARC TX.
✅ Introduced power-aware verification practices (UPF), later adopted by other teams.
✅ Reduced debug effort by 30% via optimized checkers & regression automation.
✅ Recognized as the go-to engineer for HDMI/eARC verification expertise, consistently ensuring zero major escapes to silicon.

CommunicationAPBHDMI VerificationVerification

ASIC Digital Design Engineer 1

Dec 2019 – Nov 2021 · 1 yr 11 mos · Noida, Uttar Pradesh, India

Communication

Ambient scientific

2 roles

Design Engineer

Jun 2019 – Dec 2019 · 6 mos · Bengaluru, Karnataka, India

Conducted chip sanity tests, code coverage, and fixed compile-time issues.
Developed SPI sequences, SPI BFM, JTAG BFM, and automation scripts in Python.
Built UVM-based environment for block-level verification with functional coverage.
Integrated SPI into UVM TB; validated accumulator counter with functional coverage.
Key Achievements:
✅ Successfully transitioned verification flow from basic to UVM-based methodology.
✅ Developed multiple reusable BFMs, reducing effort in subsequent projects.
✅ Recognized as an early-career engineer who drove measurable efficiency gains.

CommunicationAPB