Jan 2020 – Aug 2021 · 1 yr 7 mos · Noida, Uttar Pradesh, India · On-site

• 1) Developed a new Engineering Change Order flow to reduce compile time by up to 75% on large designs with identical results. The first RTLC run marks modules; the second run compiles only those with advisor-recommended optimizations, avoiding full RTLC re-run.
• 2)Developed and modified various existing features for Mentor graphics Veloce Emulator Platform and unit testing.
• 3)Optimizing the critical path analysis, performance and capacity requirements of the tool.
• 4) Developed a Homogeneous Template Merging flow to reduce macro wastage caused by small-size templates. Previously, mapping small templates to macros led to capacity loss. This flow merges smaller templates into larger ones, optimizing macro usage and minimizing capacity overhead.
• 5) Optimizing Advisor Flow to Reduce RTLC Compile Time . Enabled reuse of advisor feedback for minor design changes, achieving similar capacity/performance with a single RTLC run. it avoids RTLC 2nd Re run.
• 6) Implemented hierarchical instance-specific path flow optimization in RTLC,enhancing capacity and performance through user-specified hierarchical paths.
• 7) Leveraged a range of RTL Compiler optimizations including module flattening, retiming, constant propagation, delay mapping, memory dissolution, logic replication, resource sharing, FSM encoding, dead code elimination, operator balancing, and pipeline restructuring to improve capacity, performance, and timing closure in large-scale designs.
• 8)Extending various methodologies for various applications and flows.
• 9) solved top end critical customer issues within strict deadlines.
• 10)Developing testcase suite/testbenches and enhancing regression setup for better bug findings at early stage of development

Oct 2018 – Jan 2020 · 1 yr 3 mos · Noida Area, India

• 1) Hands on Design/ development in C++ for product "Veloce Emulator", RTL compiler Optimisation Team
• 2) Added support for unrolling loop Optimisation (ex: for-if , do while loops) for optimize netlist.
• 3) Developed flow for 4:1 Mux implementation using 3 LUTS instead of 2 LUTS. when sig is connected to 'Q' pin of flops.
• 4) Data enginerring applied on RTL complier to reduce compile time.
• 5) Developed flow for pipeline Annotation from scratch which helps to improve performance, via retiming, by inserting pipeline flops at user identified locations.

Jul 2015 – Sep 2018 · 3 yrs 2 mos · Gurgaon, India · On-site

• Worked in Indian startup as a Software Development of Application for Central Battery Management System (CBMS).Developed product from scratch and worked on each stage to release the product.
• Developed Application for a Battery Management System for controlling and monitoring Li-Ion cell voltages and temperatures.
• Developed Bootloader for the CBMS Product.
• Various Modification at stack level to add functionalities and required features not provided by stack.
• Enhanced existing systems by adding USB 2.0 functionality.