Sai Krishna Garlapati

Software Engineer

Hyderabad, Telangana, India3 yrs 9 mos experience

Highly Stable

Key Highlights

Expertise in high-speed SerDes interface IP verification.
Proficient in UVM/VMM test environments for complex protocols.
Strong background in debugging and enhancing verification processes.

Stackforce AI infers this person is a Semiconductor Verification Engineer with strong skills in high-speed interface protocols.

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Skills

Core Skills

Silicon DesignVerificationWeb Development

Other Skills

AMBA AXIPCIe protocolUVMSystem VerilogPhysical layer knowledge of PCIe ProtocolSerDesFunctional coverageVMMDebuggingRTL VerificationConstrained randomized stimuliJavaScriptFront-end Web Development - AngularAngularAssertion Based Verification

About

Experienced design verification engineer with strong background working on high-speed SerDes interface IP predominantly supporting protocols PCIe Gen 1 through Gen 7, ethernet and several others like USB, SATA etc. Skilled in debugging and developing coverage-driven constrained randomized UVM/VMM test environments. Knowledgeable in PCIe, ethernet, AXI protocols. Currently working on verification of Networking SoCs at AMD.

Experience

3 yrs 9 mos

Total Experience

3 yrs 4 mos

Average Tenure

5 mos

Current Experience

Amd

Senior Silicon Design Engineer

Jan 2026 – Present · 5 mos · Hyderabad, Telangana, India · On-site

AMBA AXISilicon Design

Synopsys inc

3 roles

ASIC Digital Design, Senior Engineer

Promoted

Jan 2024 – Dec 2025 · 1 yr 11 mos · On-site

Worked on verifying the SerDes PHY IP for PCIe Gen 6, 7 protocols using a UVM test bench with individual functional block-level verification.
Bringing up new tests for verifying RTL enhancements.
Enhancing the Test bench with new System Verilog assertions and bug fixes.
Physical layer knowledge of PCIe Protocol
Worked on 56G Ethernet PHY and its features like Auto-negotiation and Link training.

PCIe protocolVerification

ASIC Digital Design, Engineer

Jul 2022 – Dec 2023 · 1 yr 5 mos · On-site

Worked on verifying multi-protocol (prominently PCIe Gen 1-5, Ethernet etc.) 32G Serdes PHY IP with a VMM test bench, debugged and fixed a slew of Test bench issues and helped in identifying several RTL bugs.
Brought up test bench enhancements for verifying major RTL feature implementations.
Debugging and root causing functional and firmware issues.
Gained experience in functional coverage.

SerDesFunctional coverageVerification

ASIC Digital Design, Technical Intern

Jan 2022 – Jun 2022 · 5 mos · On-site

Having a head start to my career in the VLSI industry as a verification engineer, I worked on verifying the 32G SerDes interface PHY IP through the standard UVM and VMM test benches with constrained randomized stimuli and industry standard EDA tools like Synopsys VCS and Verdi.

SystemVerilogRTL VerificationVerification

Opennets

Frontend Developer

May 2021 – Jul 2021 · 2 mos · Marathahalli, ORR, Bengaluru, Karnataka

Worked as a Front-end developer on a Data Network traffic simulation software for spine leaf topology, using angular framework. Collaborated with a back-end team and developed the full stack.

JavaScriptFront-end Web Development - AngularWeb Development