Varun Shanker Trivedi — Software Engineer
I am a Staff / Senior ASIC Verification Engineer with 7+ years of experience in IP, Sub-System, and SoC-level verification, working across complex, multi-client project environments. I have a strong understanding of end-to-end verification architecture, from test-plan analysis to coverage closure. My expertise lies in building robust UVM-based verification environments using SystemVerilog, with a strong focus on debugging complex environment issues, protocol-level corner cases, and functional failures. I have hands-on experience working with both HVL and C-based test scenarios, and I actively contribute to improving verification quality and regression stability. I have worked extensively on high-speed and industry-standard protocols, including PCIe (Gen3–Gen5), CXL, UCIe, APB, I2C, MIPI-CSI2, and Ethernet (10G/25G/100G). I am comfortable analyzing protocol behavior, identifying missing scenarios, and translating specifications into executable test cases. 🔹 Core Expertise: • UVM/OVM-based testbench development (SV) • IP / Sub-System / SoC verification • Test-case development, regression execution & analysis • Functional & code coverage analysis and closure • Assertion development and debug support • Debugging using VCS, Verdi, QuestaSim • Version control: Git, Perforce, ClearCase, SVN • UNIX/Linux-based verification workflows I am known for my strong debugging mindset, ability to identify verification gaps, and for collaborating effectively with design, validation, and cross-site teams. I enjoy working on technically challenging problems and continuously improving verification efficiency and quality. 💡 Open to connecting with engineers, architects, and recruiters globally, and always interested in discussing advanced verification challenges, high-speed interconnects, and global opportunities.
Stackforce AI infers this person is a highly skilled ASIC Verification Engineer specializing in high-speed interconnects and complex verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 7 mos
Career Highlights
- 7+ years in ASIC verification across multi-client projects.
- Expert in UVM-based verification environments using SystemVerilog.
- Strong debugging mindset with a focus on verification quality.
Work Experience
Synopsys Inc
ASIC Digital Design Staff engineer (1 yr 9 mos)
Synopsys India Pvt. Ltd.
Application Specific Integrated Circuit Engineer (1 yr 9 mos)
eInfochips (An Arrow Company)
Senior Verification Engineer (8 mos)
eInfochips Pvt. Ltd.
Senior Validation Engineer (8 mos)
Intel Corporation
Pre Si Validation/Verification Engineer (1 yr 6 mos)
Intel India Pvt. Ltd.
Validation Engineer (1 yr 6 mos)
Cerium Systems
Design Verification Engineer (9 mos)
Validation Engineer (9 mos)
SiSoC Semiconductor Technologies Pvt Ltd.
Verification Engineer (2 yrs 11 mos)
Validation Engineer (2 yrs 10 mos)
Education
PGD VLSI at CDAC ACTS PUNE
Bachelor's degree at ambalika institute of management and technology
PGDVLSI at CDAC PUNE
PGDVLSI at C-DAC ACTS - Pune
Bachelor of Technology at Dr. A.P.J. Abdul Kalam Technical University