V

Varun Shanker Trivedi

Software Engineer

Bengaluru, Karnataka, India7 yrs 7 mos experience
Most Likely To Switch

Key Highlights

  • 7+ years in ASIC verification across multi-client projects.
  • Expert in UVM-based verification environments using SystemVerilog.
  • Strong debugging mindset with a focus on verification quality.
Stackforce AI infers this person is a highly skilled ASIC Verification Engineer specializing in high-speed interconnects and complex verification methodologies.

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Skills

Other Skills

Data VerificationEtherNet/IPRegression TestingVirtual ServerRemote User TestingValidation Reports10G EthernetWorking with System IntegratorsHigh Speed InterfacesCCH IntelliconnectResponsys InteractClearCaseProtocol AnalysisRTL VerificationI/O Virtualization

About

I am a Staff / Senior ASIC Verification Engineer with 7+ years of experience in IP, Sub-System, and SoC-level verification, working across complex, multi-client project environments. I have a strong understanding of end-to-end verification architecture, from test-plan analysis to coverage closure. My expertise lies in building robust UVM-based verification environments using SystemVerilog, with a strong focus on debugging complex environment issues, protocol-level corner cases, and functional failures. I have hands-on experience working with both HVL and C-based test scenarios, and I actively contribute to improving verification quality and regression stability. I have worked extensively on high-speed and industry-standard protocols, including PCIe (Gen3–Gen5), CXL, UCIe, APB, I2C, MIPI-CSI2, and Ethernet (10G/25G/100G). I am comfortable analyzing protocol behavior, identifying missing scenarios, and translating specifications into executable test cases. 🔹 Core Expertise: • UVM/OVM-based testbench development (SV) • IP / Sub-System / SoC verification • Test-case development, regression execution & analysis • Functional & code coverage analysis and closure • Assertion development and debug support • Debugging using VCS, Verdi, QuestaSim • Version control: Git, Perforce, ClearCase, SVN • UNIX/Linux-based verification workflows I am known for my strong debugging mindset, ability to identify verification gaps, and for collaborating effectively with design, validation, and cross-site teams. I enjoy working on technically challenging problems and continuously improving verification efficiency and quality. 💡 Open to connecting with engineers, architects, and recruiters globally, and always interested in discussing advanced verification challenges, high-speed interconnects, and global opportunities.

Experience

7 yrs 7 mos
Total Experience
1 yr 5 mos
Average Tenure
1 yr 9 mos
Current Experience

Synopsys inc

ASIC Digital Design Staff engineer

Sep 2024Present · 1 yr 9 mos · India · Hybrid

Synopsys india pvt. ltd.

Application Specific Integrated Circuit Engineer

Sep 2024Present · 1 yr 9 mos

  • Owning end-to-end verification of UCIe Die-to-Die Controller IP including control plane, sideband interface, and datapath functionality.

Einfochips (an arrow company)

Senior Verification Engineer

Dec 2023Aug 2024 · 8 mos · Noida, Uttar Pradesh, India

Einfochips pvt. ltd.

Senior Validation Engineer

Dec 2023Aug 2024 · 8 mos

  • Performed subsystem-level verification of SoC interconnects, debugging integration issues across multiple IP blocks and validating protocol compliance during system integration.

Intel corporation

Pre Si Validation/Verification Engineer

Jun 2022Dec 2023 · 1 yr 6 mos · Bengaluru, Karnataka, India

Intel india pvt. ltd.

Validation Engineer

Jun 2022Dec 2023 · 1 yr 6 mos

  • Worked in Intel PSG on verification of Ethernet MRIP IP supporting multiple bandwidth configurations.

Cerium systems

2 roles

Design Verification Engineer

Sep 2021Jun 2022 · 9 mos

  • Work for Coverage Analysis, Assertion based errors debugging, Regression running, Editing and creating the sequence from scratch, worked for scripting related issues related with project.

Validation Engineer

Sep 2021Jun 2022 · 9 mos

  • Contributed to verification of multiple Intel IP subsystems including MRAM controller and PCIe/CXL based I/O virtualization features, using SystemVerilog/UVM based verification methodologies.

Sisoc semiconductor technologies pvt ltd.

2 roles

Verification Engineer

Oct 2018Sep 2021 · 2 yrs 11 mos

Validation Engineer

Oct 2018Aug 2021 · 2 yrs 10 mos

  • Worked on multiple IP verification projects including PCIe, MIPI CSI-2 and mobile display subsystem, using SystemVerilog/UVM based verification methodologies.

Education

CDAC ACTS PUNE

PGD VLSI — VLSI

Jan 2018Jan 2018

ambalika institute of management and technology

Bachelor's degree

Jan 2012Jan 2016

CDAC PUNE

PGDVLSI — VLSI

Jan 2018Jan 2018

C-DAC ACTS - Pune

PGDVLSI

Dr. A.P.J. Abdul Kalam Technical University

Bachelor of Technology

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