T

Tej P.

Software Engineer

Bengaluru, Karnataka, India10 yrs 2 mos experience

Key Highlights

Expertise in IC and Memory Layout Design.
Strong background in Semiconductors and EDA tools.
Proven track record in complex layout designs.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in IC layout and memory design.

Contact

Skills

Core Skills

Ic LayoutSemiconductors

Other Skills

Memory Layout DesignCadence VirtuosoLayout Versus Schematic (LVS)Analog Layout DesignIO layout designLinuxDesign Rule Checking (DRC)SimulationsCircuit DesignVLSIICVerilogPerlbackend designingIntegrated Circuit Design

About

Experienced Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Semiconductors, Perl, Integrated Circuits (IC), layout design,lvs & DRC. Strong engineering professional with a Bachelor of Technology (B.Tech.) focused in electronic & communication from Bundelkhand University jhansi.

Experience

10 yrs 2 mos

Total Experience

2 yrs 2 mos

Average Tenure

1 yr 3 mos

Current Experience

Synopsys inc

Staff Engineer

Mar 2025 – Present · 1 yr 3 mos · Bengaluru, Karnataka, India · On-site

Staff Engineer,Memory Layout Design

Memory Layout DesignIC LayoutSemiconductors

Hcltech

Technical Team Lead

Oct 2022 – Mar 2025 · 2 yrs 5 mos · Bengaluru, Karnataka, India · On-site

Cadence VirtuosoLayout Versus Schematic (LVS)IC LayoutSemiconductors

Altran

Senior Layout Design Engineer

Nov 2019 – Oct 2022 · 2 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Cadence VirtuosoLayout Versus Schematic (LVS)IC LayoutSemiconductors

Album semiconductors

Associate Design Engineer

Oct 2018 – Aug 2019 · 10 mos · bangalore

Spontey

Design Engineer

Jun 2014 – Mar 2017 · 2 yrs 9 mos · Bengaluru, Karnataka, India · On-site

Memory and Analog Layout Design such as SRAM,Register file memory ,GPIO,SERDES etc

Education

Bundelkhand University jhansi

Bachelor of Technology (B.Tech.) — electronic & comunication

Jan 2010 – Jan 2014

C.M.S Inter College Balrampur

Intermediate — PCM

Jan 2006 – Jan 2008

Stackforce found 100+ more professionals with Ic Layout & Semiconductors

Explore similar profiles based on matching skills and experience

Sushil Sirsat

Research Scholar

at Visvesvaraya National Institute of Technology

India12 yrs 7 mos exp

Analog Integrated Circuit DesignSignal Integrity

ABHINANDAN .

Analog Design Engineer (External)

at Synopsys Inc

Una, India2 yrs exp

Analog Circuit Design

Vijayalaxmi Raddiyavar

SRAM library validation

at Intel

Bengaluru, India4 yrs 6 mos exp

SRAMLibrary ValidationComponent DesignPDK ValidationSimulation

Sheik Abdullah

Senior Staff Application Engineer - SERDES IP

at Synopsys Inc

Bengaluru, India16 yrs 5 mos exp

Semiconductor IPTechnical RequirementsEDA

Ragadeep Bezawada

Principal Engineer

at TSMC

San Jose, United States14 yrs 4 mos exp

Physical DesignASICCPU DesignPnR (Place and Route)GSP Processor Expertise

Vyasa Maharshi Grandhi

Senior Member of Technical Staff -SoC Design Lead

at CspeedIO, Inc.

Bengaluru, India11 yrs 8 mos exp

SoC DesignRTL Design

Gudi Venkata Sai Praveen

Senior Member of Technical Staff

at Siemens EDA (Siemens Digital Industries Software)

Gopavaram, India2 yrs 10 mos exp

RTL DesignInterlakenEthernetComputer ArchitectureEmbedded Systems

Shanie George

Sr Director R & D

at Synopsys Inc

San Francisco, United States24 yrs 11 mos exp

Library ArchitectureProject ManagementStandard Cell Design