V

Vishnu Vardhan

Software Engineer

Bengaluru, Karnataka, India6 yrs experience
Highly Stable

Key Highlights

  • Expert in DFT and ASIC design methodologies.
  • Proficient in scan design and JTAG protocols.
  • Strong background in simulations and debugging.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in DFT methodologies.

Contact

LinkedIn

Skills

Core Skills

Scan InsertionAutomatic Test Pattern Generation (atpg)

Other Skills

CompressionMbistSimulationsOCCTcl-TkVerilogDigital ElectronicsJoint Test Action Group (JTAG)CMOS

About

Knowledge on DFT, ASIC flow, scan design, scan drc's, Scan insertion, Scan compression, Boundary scan, JTAG, ATPG, OCC, TAP controller, MBIST, Simulations and debugging.

Experience

6 yrs
Total Experience
1 yr 7 mos
Average Tenure
1 yr 1 mo
Current Experience

Amd

Senior Silicon Design Engineer

May 2025 – Present · 1 yr 1 mo · Bangalore Urban, Karnataka, India

Scan InsertionCompressionAutomatic Test Pattern Generation (ATPG)MbistSimulationsOCC+5

Microchip technology inc.

DFT Engineer

Apr 2022 – May 2025 · 3 yrs 1 mo · Bengaluru, Karnataka, India

Skandysys private limited

DFT Engineer

Apr 2021 – Mar 2022 · 11 mos · Bangalore Urban, Karnataka, India

Vlsiguru training institute

Trainee

Jun 2019 – May 2020 · 11 mos · Bangalore

Education

Sree

Bachelor of Technology - BTech

Jan 2015 – Jan 2019

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