Jun 2018 – Mar 2023 · 4 yrs 9 mos

• Worked on Gated Clock Conversion (GCC) and new feature on extending gcc(EGCC) yo whole design using Clock Control IPs. Introducing flows of Clock Impact analysis to improve the performance of overall EGCC prototype solution.
• Started Working on Partitioner and specifically timing aspect of Partitioner. Improving the QOR and correlation of results has been the primary focus.

Jun 2016 – Jun 2018 · 2 yrs

• 1. Worked to make FPGA synthesis solution- Synplify - CDC aware.
• 2. Working on Clock Tree Extraction and Clock Tree Visualization for Synopsys Prototyping Product Protocompiler in order to expedite the TTFP.

Feb 2015 – May 2016 · 1 yr 3 mos

• Internal Switch to work on evolving product VC-CDC in Synpsys Static Verification Product.
• Developed Reset Domain Crossing Solution in Synopsys Static Verification Product within very aggressive deadline.
• Switched to work on VC-Low Power Product after Attrenta aquisition of Synopsys - Refactored complex code and wrote the JSON writer for dumping data.

Jun 2010 – Feb 2015 · 4 yrs 8 mos

• Part of High Level synthesis development team for Synplify FPGA product.
• Worked on numerous features and optimizations on Xilinx, Microsemi, Achronix and core internal mapper involving combinational & sequential logic, ALUs, RAMs and DSP Blocks.
• Complete ownership of Microsemi and Achronix OEM Mapper activities. Responsible for planning, execution and delivery of release items, ensuring customer success. Successful renewal of multi-million dollar OEM contracts every time.
• Incorporated new techniques to ensure logic correctness in DSP and RAM mapping. Built prototype mapper with unconventional deviation from traditional FPGA architecture requiring change in core logic mapping algorithm.
• Involved in grooming junior developers, recruiting new developers and involved in decision making regarding introduction of a process or technology in the product
• Awarded Project Excellence Award for improving the QoR of Achronix mapper.

May 2008 – May 2010 · 2 yrs

• Part of High Level synthesis development team for Synplify FPGA product.
• Worked on numerous features and optimizations on Xilinx and Achronix mappers involving combinational & sequential logic, ALUs, RAMs and DSP Blocks.
• Sole ownership of all Achronix OEM mapper activities involving drafting of requirement & implementation specifications, code writing, unit testing, communication with testing team and OEM partner, and making regular releases to the customer satisfaction . Introduced new optimizations unique to Achronix PicoPIPE architecture. Introduced the support for Achronix DSP inference from scratch. Successful renewal of Achronix OEM contract every time.
• Awarded Spot Excellence Award for efforts beyond call of duty.

Oct 2007 – May 2008 · 7 mos · Bangalore, India

• Part of High Level synthesis development team for Synplify FPGA product.
• Built a successful prototype for RTL to C-output and proved the concept-correctness.

Feb 2007 – Sep 2007 · 7 mos · Noida, India

• Part of development team of a new tool, now commercialized.
• Worked on Chip finishing and Open Access. Developed an abstract checker for better visualization of design faults and worked on making database compatible with Open Access standards.

Jul 2005 – Dec 2006 · 1 yr 5 mos · Bangalore, India

• Part of Samsung's core IMS team.
• Worked on development as well testing to ensure successful completion and commercialization of IP Multimedia Sub-system(IMS) services on Samsung mobile handsets for American GSM and CDMA networks provided by Cingular and Verizon. Ownership of ISIM (IMS-SIM) authentication and enhancement of SIP stack as part of entire solution.
• Awarded Business Contribution Award for the IMS Development Work.