Ajith Kumar R — Software Engineer
STA Engineer 1.Top/Block timing closure 2.SDC development 3.IP constraints (LPDDR,ComPHY) 4.DFT Timing
Stackforce AI infers this person is a VLSI Design Engineer with expertise in STA and timing closure.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 1 mo
Skills
- Sta Engineering
- Timing Closure
Career Highlights
- Expert in STA Engineering and Timing Closure.
- Proficient in SDC development and IP constraints.
- Strong foundation in VLSI Design from a reputed institution.
Work Experience
Marvell Semiconductor
STA Engineer (6 yrs 9 mos)
GLOBALFOUNDRIES
STA Engineer (1 yr 4 mos)
Intern (3 mos)
Education
MTech at Vellore Institute of Technology
BTech at College of Engineering , Munnar
at Sabarigiri school of Education, Punlaur, Kollam
