Onkar Sanjay Mane — Software Engineer
I am Onkar Mane, a passionate Physical Design Engineer with hands-on experience in the complete RTL to GDSII design flow, gained through my ongoing internship at Siemens EDA. My expertise lies in optimizing designs for Power, Performance, and Area (PPA) using advanced techniques such as Static Timing Analysis (STA), power optimization, and low-power methodologies, including clock gating, power gating, and multi-VT technologies. I am proficient in TCL scripting, which I have utilized to automate key design tasks in physical design, including floorplanning, placement, clock tree synthesis (CTS), routing, and GDS file generation across technology nodes ranging from 45nm to 5nm. My technical skill set also extends to tools like Siemens APRTL, AMD Xilinx Vivado, and LTspice. In addition to my technical acumen, I have demonstrated leadership and teamwork skills in various extracurricular activities, such as leading a team at ROBOCON and mentoring students at IIT Kanpur. I am driven by the challenge of designing efficient, high-performance, low-power systems and continuously expanding my knowledge in VLSI design and ASIC design methodologies. Skills: RTL to GDSII Flow | TCL Scripting | ASIC Design | STA | Low Power Design | Power Optimization Siemens APRTL | Siemens APRISA | Xilinx Vivado | LTspice | Simulink | Multisim Verilog | C/C++ | MATLAB | Assembly Language Current Focus: Currently, I am focusing on enhancing my expertise in physical design, with an emphasis on power and timing optimization techniques. I am always open to learning new technologies and collaborating with industry experts to contribute to innovative solutions in the semiconductor field. Feel free to connect with me or reach out to discuss exciting opportunities in VLSI, ASIC design, or semiconductor technologies! #PhysicalDesignEngineer #RTLtoGDSII #PPA #PowerOptimization #TCLScripting #StaticTimingAnalysis #LowPowerDesign #ClockGating #PowerGating #MultiVT #SiemensEDA #VLSIDesign #ASICDesign #Semiconductors #EDATools #SiemensAPRTL #SiemensAPRISA #XilinxVivado #Leadership #Teamwork #ChipDesign #VLSI #DigitalDesign
Stackforce AI infers this person is a Semiconductor and IoT specialist with expertise in VLSI and ASIC design.
Location: Bengaluru, Karnataka, India
Experience: 1 yr 1 mo
Skills
- Physical Design
- Static Timing Analysis
- Rtl To Gdsii
- Low Power Design
- Embedded Systems
- Project Management
Career Highlights
- Expert in RTL to GDSII design flow and optimization.
- Proficient in TCL scripting for automation in physical design.
- Demonstrated leadership in team projects and mentoring.
Work Experience
Qualcomm
Engineer (1 mo)
Alphawave Semi
ASIC Design Engineer I (1 yr)
Siemens EDA (Siemens Digital Industries Software)
Internship - Physical Design Engineer (10 mos)
Earth LogicWare Technologies - India
Intern | Embedded Design Engineer | computer Architecture | Hardware Design | Digital Design (1 mo)
Education
Master of Technology - MTech at Indian Institute of Technology, Kanpur
Bachelor of Technology - BTech at Government College of Engineering Karad