Hoang Nguyen Huy

Software Engineer

Ho Chi Minh City, Vietnam3 yrs experience
Highly Stable

Key Highlights

  • Expert in Layout Design and DRC methodologies.
  • Hands-on experience with advanced semiconductor projects.
  • Strong collaboration with circuit design teams.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in layout and circuit design.

Contact

LinkedIn

Skills

Core Skills

Design Rule Checking (drc)Layout Versus Schematic (lvs)Layout Design

Other Skills

Field-Programmable Gate Arrays (FPGA)Embedded C/C++ ProgrammingSystemVerilogElectronic Circuit Design

Experience

3 yrs
Total Experience
3 yrs
Average Tenure
3 yrs
Current Experience

Synopsys inc

3 roles

Senior Layout Engineer

Feb 2025 – Present · 1 yr 4 mos · Ho Chi Minh City, Vietnam

Design Rule Checking (DRC)Layout Versus Schematic (LVS)

Layout Design Engineer

Jun 2023 – Feb 2025 · 1 yr 8 mos · Ho Chi Minh City, Vietnam

  • ​Executed a UCIE project design flow similar to the Synopsys Custom Compiler workflow.
  • ​Designed layouts for control logic cells and critical high-speed cells, specifically targeting clock and differential signals (gen 1&2)
  • ​Collaborated with circuit designers to verify and commit post-simulation performance.
  • ​Managed release package generation and prepared QA packages for final release
Layout DesignDesign Rule Checking (DRC)

Intern (Technical-Engineering)

Nov 2022 – Jun 2023 · 7 mos · Ho Chi Minh City, Vietnam

  • Capstone Project: LVDS Transmitter Using 14nm CMOS Technology
  • Trained on CMOS Fundamentals, Circus Analysis, Fabrication Process, Layout Effect, Timing Analysis
  • Familiar with Synopsys EDA tools

Education

RMIT University Vietnam

Bachelor of Engineering - BE — Electrical and Electronics Engineering

Oct 2019 – Apr 2024

Stackforce found 100+ more professionals with Design Rule Checking (drc) & Layout Versus Schematic (lvs)

Explore similar profiles based on matching skills and experience

Sourav Sharma

Sourav Sharma

Member of Technical Staff

at Oracle

Greater Delhi, India7 yrs 8 mos exp
CC++JavaScriptREST APIs
Sushil Sirsat

Sushil Sirsat

Research Scholar

at Visvesvaraya National Institute of Technology

India12 yrs 7 mos exp
Analog Integrated Circuit DesignSignal Integrity
Varun Kumar

Varun Kumar

Synthesis/STA Engineer (Contractor)

at AMD

Hyderabad, India1 yr 1 mo exp
Integrated Circuit DesignPhysical Design
Devaraj N

Devaraj N

Senior Mobile Developer

at Amazon

Bengaluru, India9 yrs 10 mos exp
iOS DevelopmentMobile Application Development
Vijayalaxmi Raddiyavar

Vijayalaxmi Raddiyavar

SRAM library validation

at Intel

Bengaluru, India4 yrs 6 mos exp
SRAMLibrary ValidationComponent DesignPDK ValidationSimulation
Chaitanya Kumar Madineni

Chaitanya Kumar Madineni

Graphics Hardware Engineer

at Intel Corporation

Bengaluru, India11 yrs 10 mos exp
Physical DesignGraphics Hardware EngineeringTiming Closure
Deepakshi Tyagi

Deepakshi Tyagi

Lead Technical Communications Engineer

at Cadence Design Systems

Bengaluru, India9 yrs 8 mos exp
Technical WritingDocumentationPhysical Design EngineeringProduct DevelopmentApplication Engineering
Gudi Venkata Sai Praveen

Gudi Venkata Sai Praveen

Senior Member of Technical Staff

at Siemens EDA (Siemens Digital Industries Software)

Gopavaram, India2 yrs 10 mos exp
RTL DesignInterlakenEthernetComputer ArchitectureEmbedded Systems