Nishanta B.

Software Engineer

Noida, Uttar Pradesh, India4 yrs 10 mos experience

Key Highlights

Led significant performance improvements in EDA tools.
Successfully integrated advanced power management strategies.
Achieved a 30% faster compilation time in compiler development.

Stackforce AI infers this person is a highly skilled EDA engineer with expertise in low power systems and compiler development.

Contact

nishanta.boro12@gmail.com LinkedIn

Skills

Core Skills

Low Power SystemsC++SystemverilogCompilers

Other Skills

Performance AnalysisCMakeProblem SolvingAlgorithmsStandard Template Library (STL)EDAUnified Power Format (UPF)LibertyIntel TBBMultithreadingBoost (C++ libraries)Mixed-Signal Integrated CircuitsPerforceCadence Schematic CaptureCadence Virtuoso

Experience

4 yrs 10 mos

Total Experience

2 yrs 8 mos

Average Tenure

2 yrs 2 mos

Current Experience

Cadence design systems

Lead Software Engineer

Apr 2024 – Present · 2 yrs 2 mos · Noida, Uttar Pradesh, India · Hybrid

Working on Virtuoso Power Manager, a formal Low Power verification signoff tool for Analog Mixed-Signal Design

C++Low Power Systems

X-epic

3 roles

Senior Engineer I | R&D

Oct 2023 – Mar 2024 · 5 mos

Led a team of four from the India site to collaborate with the Low Power Team for Galaxsim, a simulator product developed by X-EPIC. This collaboration resulted in an overall ~40% improvement in performance for UPF Elaboration through performance analysis using Oracle Analyzer. Additionally, visited the Shanghai HQ to work more closely with the overseas team, fostering better communication and collaboration.

SystemVerilogSystem Verilog

Engineer II | R&D

Jul 2021 – Oct 2023 · 2 yrs 3 mos

As the Team Lead for the Low Power Team at Galaxsim, I successfully implemented advanced power management strategies for simulation and conducted rigorous R&D testing, developing comprehensive test cases from UPF LRM.
In my capacity as the Lead for the Frontend Project at the India site, I oversaw the integration of an open-source RTL compiler with our in-house synthesis tool. This initiative resulted in a significant improvement in pass rates, from approximately 10% to 90% within five months, and optimized performance by 20%.
As the Research Project Lead for Netlist Compiler Development, I designed a lightweight database for efficient Netlist storage and developed a lexx and yacc-based compiler. This development achieved a 30% faster compilation time compared to our existing in-house compiler.
My individual contributions include providing critical support for XMR/Cross-Module References in the in-house synthesis tool and implementing Levelization and Dead Logic Elimination in Netlist, thereby enhancing the overall performance and reliability of our tools.

CMakeCompilers