Sep 2015 – Oct 2017 · 2 yrs 1 mo · Greater Bengaluru Area

• As part of GAL (Graphics Architecture Lab), joined as responsible to manage Platform Execution team (team strength of 6 ) and primary focuses were on to bring up the Silicon platform for Graphics Perf and Power analysis, Performance debug with micro kernels, Lab infrastructure and process development.
• Effective roles handled :
• a) Workloads for GPU perf analysis
• b) Defined workloads for S-Curve analysis
• c) Part of Bring-up team and represented GAL in Silicon bring-up
• d) Graphics workloads Perf/W analysis for activity factor tuning and feedback to DCVS for frequency profile
• e) Tools and Methodology ownership for GAL activities
• f) scope out for tear down experiments on competitive devices
• g) Lab budgeting and CAPEX requirements responsibility
• Part of Graphics Architecture Team - Responsible for Compute workload analysis on Silicon and feedback on performance features for "N+1" Architecture.

Mar 2007 – Sep 2015 · 8 yrs 6 mos · Bengaluru, Karnataka, India · On-site

• Joined in MCP division Memory Compatibility and Validation group (as part of Systems Engineering). Responsible to define the test suite and test plan for running concurrency test cases across the PVT corners and summarize the memory vendor results for MCH validation results which gets published in NV website for customer review.
• In the year 2009 - The MCP division merged with GPU Chip solutions team and started the small team and new function for Post-Silicon Power and Performance Characterization efforts. Led the team to define the process, methodology, execution flow, including lab process. It led to the responsibility on below items and successfully grown up the team with more headcounts. (Architecture : Fermi, Kepler, Maxwell and Pascal)
• a) TDP (Thermal Design Power) and EDP (Electrical Design Point) definition on Post-Silicon - Key inputs for Silicon binning and effective SKU definition for better yield results.
• b) Post-Silicon based Power calculator with performance benchmarks and used internal process for binning and SKU definition
• c) PDN limitation analysis and definition based on EDP measurement process (as merged Desktop and Notebook chip solutions)
• d) Power Estimator tool correlation with Post-Si measurements and input for N+1 ARCH corrective ness
• e) Part of competitive platform tear down analysis
• f) Responsible for Leakage calculator and accuracy tuning (for real time leakage calculation and limit within TDP budget)
• g) Responsible for Wide Area Testing process and methodology definition
• h) GPU Power feature characteriztion and power budget analysis for DCVS, Thermal and binning process.

Mar 2004 – Mar 2007 · 3 yrs · Puducherry, India · On-site

• a) Responsible for Material IQC (Incoming Quality Control) and FQC (Final Quality Check)
• b) Management Representative for ISO 9001:2000 certification process for System Integration process (BVQI)
• c) Successfully implemented the Lean Manufacturing concept in System Integration line
• d) Technical training coordinator for Internal Product definition team
• e) Lead the PEG (Product Engineering Group) to address Desktop and Server tender process
• f) Implemented the automation process to capture System Integration state update in the manufacturing process

Apr 2000 – Mar 2004 · 3 yrs 11 mos · Puducherry, India

• a) Reliability Engineering for MTBF calculation inside PC components.
• b) Process Quality Assurance including Technical POC for customer satisfaction cell
• c) ISO 9001:2000 Process quality Coordinator for internal audits and certification
• d) Six Sigma and Lean Manufacturing - Process definition in production line
• e) POC for Direct Sales Organization (DSO) to Manufacturing process for product quality