Dr. Sourav Nath

AI Researcher

Silchar, Assam, India11 yrs 7 mos experience

Key Highlights

  • Over 10 years of expertise in VLSI CAD tools.
  • Successfully taped out 3 ASIC chips in SCL 180nm technology.
  • Passionate about innovative solutions in analog circuit design.
Stackforce AI infers this person is a VLSI and Analog Circuit Design expert in the semiconductor industry.

Contact

Skills

Core Skills

Analog Circuit DesignAnalog LayoutAnalog Chip Tape-outMixed-signal Ic DesignChip TapeoutHigher Education TeachingAnalog Integrated Circuit Design

Other Skills

Cadence VirtuosoCadence Virtuoso Layout EditorCadence SpectreCadence EncounterGuest LecturingVHDLXilinx ISEXilinx VivadoField-Programmable Gate Arrays (FPGA)Software DevelopmentPythonProgrammingSoftware EngineeringMySQLC#

About

🔌 Experienced Lab Engineer | Analog Circuit Designer | VLSI CAD Specialist 🛠️ Adept at Low-Power, Low-Noise OTA Design for Biomedical Applications 🔬 Contributed to MeitY Funded Projects at IIT Madras and NIT Silchar 🧰 Over 10 Years of Expertise in VLSI CAD Tools Installation & Analog Design and Simulation. 🧩 Successfully Taped Out 3 ASIC Chips in SCL 180nm Technology. 🧩Worked in UMC180nm, TSMC65nm, UMC65nm, and SCL180nm Technology Node. Passionate about pushing the boundaries of technology and creating innovative solutions in analog circuit design. Excited to connect with like-minded professionals and explore opportunities for collaboration and growth in the semiconductor industry. Let's connect! 🤝 #VLSI #AnalogDesign #Semiconductor #ASIC #Biomedical #CADTools #Innovation

Experience

11 yrs 7 mos
Total Experience
3 yrs 8 mos
Average Tenure
6 mos
Current Experience

Iiest, shibpur

Post doctoral fellow

Dec 2025Present · 6 mos · On-site

  • Analog Mixed Signal Design.

National institute of technology silchar

2 roles

Project Associate-II

Sep 2025Dec 2025 · 3 mos · Silchar, Assam, India · On-site

  • Analog Circuit Design and Analog Layout folowed by Chip Tape-out
Analog LayoutAnalog Circuit DesignCadence VirtuosoCadence Virtuoso Layout Editor

Project Associate-II

Dec 2023Apr 2025 · 1 yr 4 mos · Silchar, Assam, India · On-site

  • analog circuit design and simulation, analog layout, chip tapeout
Chip TapeoutMixed-Signal IC Design

Silizium circuits

Senior Engineer

Apr 2025Jun 2025 · 2 mos · Kochi, Kerala, India · On-site

Analog LayoutAnalog chip tape-outCadence VirtuosoAnalog Chip Tape-out

Assam (central) university

Guest Faculty

Nov 2021Oct 2022 · 11 mos · Silchar, Assam, India · On-site

  • Teaching B.Tech/M.Tech Students, subjects related to VLSI Design, Analog VLSI Design Microelectronics Technology, CAD Tools Like Cadence Virtuoso.
Analog chip tape-outAnalog LayoutCadence Virtuoso Layout EditorCadence SpectreCadence EncounterGuest Lecturing+2

National institute of technology silchar

Lab Engineer

Dec 2012Oct 2021 · 8 yrs 10 mos · Silchar, Assam, India

Cadence VirtuosoCadence Virtuoso Layout EditorCadence SpectreCadence EncounterChip TapeoutAnalog Integrated Circuit Design+1

Education

National Institute of Technology Silchar

Doctor of Philosophy - PhD — Design and Analysis of Analog Frontend Circuits for Neurological Disease Detection

Jul 2020Oct 2024

National Institute of Technology Silchar

Master of Technology - MTech — Microelectronics & VLSI Design

Jan 2017Jan 2020

Sikkim Manipal Institute of Technology - SMU

Engineer's Degree — Electronics & communication Engineering

Jan 2008Jan 2011

Silchar Polytechnic Assam

Diploma In Electronics & Telecommunication Engineering — electronics

Jan 2004Jan 2007

Primrose English Medium High School.Lala

Jan 2002Present

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