Jul 2023 – Mar 2026 · 2 yrs 8 mos · Mississauga, ON · On-site

• Working in methodology team helping in enabling latest technology.
• Testing new flows and methodology.
• Layout development of high-speed standard cells.

Mar 2018 – Feb 2022 · 3 yrs 11 mos · Bengaluru, Karnataka, India

• Product line owner of 112G SERDES IP in TSMC 5nm, 7nm ,16nm and GF12(Layout).
• Product line owner of 56G SERDES IP in TSMC 16nm (Layout).
• Expert SerDes PHY sub-blocks (RX, TX, CM, VCO, PLL, CDR, DFE, CTLE, VGA
• Experience in handling layout team of 15-30 layout engineers, including resource planning, scheduling etc. Was leading a team of 15 full time employees in Synopsys

Feb 2022 – Jun 2023 · 1 yr 4 mos · Delft, South Holland, Netherlands

• Leading the Full chip layout activity.
• Collaborate closely with Design/Package and layout team.
• Leading a team of 20 members across different geographical location, including permanent and contractors.

Jan 2013 – Mar 2018 · 5 yrs 2 mos · Bangalore

• Layout owner of 14G Feedback receiver. Blocks include LNA, MIXER, TIA, ADC
• Top-level owner on 12G SERDES for PMC Sierra
• Managed staff of 20+ Layout engineers for RF-Modem applications across three locations (Munich, Bangalore, Singapore). Coordinate with internal groups (Circuit design, P&R and CAD).
• Layout owner of 10GHz PLL layout design in TSMC 65nm. Blocks include LC VCO, Fully Differential Charge Pump, Loop Filter, and Various Bias Blocks etc
• Analog Front End Layout Design for ECG and Pulse Oxy meter in TSMC 90nm
• The ECG block consists of Analog Front End Input (AFI) with20-Bit Delta Sigma Module (DSM). This block will share the substrate with other RF Blocks
• Responsible for entry level training for 3 batches of 20 to 30 people, training for other small batches. (Totally around 100 people), coordinating with other industry experts, taking 50% of training sessions, correcting assignments, making syllabus, layout content.

Jul 2011 – Jan 2013 · 1 yr 6 mos · Bangaon Area, India

• Standard Cell Library Development in UMC 20nm, TI 65nm
• Lead a team of 7 Layout Engineers. Developed the whole library and delivered to the customer according to the schedule with all the Back-end check pass and made sure the quality was met.
• Wrote skill code for creating templates and boundary checks.
• Development of High Speed IOs, LVDS IBM 28nm
• The High-speed IO Library contained 24 Different types of IOs according the circuit specification as well as area given by the customer.
• Lead the team of 8 people for developing the High speed IOs, LVDS USB and REFGEN libraries as well as developed some BIDIR’s in the library.

Oct 2009 – Jul 2011 · 1 yr 9 mos · Bangalore

• Worked on USB 2.0 & OTG Tx/Rx Design in 65nm
• USB transmitter output has custom 3.3V, and OTG have integrated 5.25V tolerant GPIO and also can be double bonded with external 5.25V tolerant GPIO pins. In case OTG feature is not used these pins can be used as GPIO pins
• Responsibility of full IP layout development, PV cleaning and EMIR. Had to take special care of effects like electro migration matching, shielding etc
• Worked on GPIO Library Development 65nm
• This IO library consists of BIDIRs IOs, Power cells, Switches, Corner cells, filler cells etc

May 2007 – Oct 2009 · 2 yrs 5 mos

• Full Chip Layout of Cypress Low Cost PSoC 130nm
• The full Chip contains 40 pads (with 4 ports of 8 bits and two of power and ground pads and rest for the test purpose)
• Responsibilities include full chip block placement, routing, IP view generation and coordination of layout works with other team viz. P&R, Circuit designers etc. The key challenge was to take special care of effects like electro migration, latch up, Shielding, Routing channel in the full chip, etc.
• 10bit SAR ADC IP Layout Development for PSoC3 Family 130nm
• Pump IP Layout Development for PSoC3 Family 130nm
• Temperature Sensor IP Layout in UMC 65nm
• IO Pad Ring Development of PSoC. The task assigned was to develop IO-Ring layout for the chip and its integration, bonding

Jul 2006 – May 2007 · 10 mos

• Worked on Kookaburra BlackFin Series DSP Processor in TSMC 90nm for Design of ESD VPP pad according to the other TSMC IO cell that meets all IO constraints
• Developed Hercules script for checking Diode between Supplies at full chip level