A

Avanish Shukla

Software Engineer

Noida, Uttar Pradesh, India13 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 13 years of experience in Memory Design/Layout.
  • Expertise in SRAM and custom circuit design.
  • Proficient in VLSI and ASIC methodologies.
Stackforce AI infers this person is a VLSI and ASIC design expert with extensive experience in memory design.

Contact

LinkedIn

Skills

Core Skills

SramLayout DesignCustom Sram Circuit DesignStandard Cell DesignCustom Design/layout

Other Skills

Circuit DesignVLSIASICDigital ElectronicsElectronicsSimulationsApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)LinuxLVSIntegrated Circuit DesignDRCCadence VirtuosoSynopsys toolsPhysical Verification

About

-13 years of experience in Memory Design/Layout

Experience

13 yrs 8 mos
Total Experience
6 yrs 10 mos
Average Tenure
8 yrs 10 mos
Current Experience

Synopsys inc

5 roles

Sr Staff Engineer

Promoted

May 2026 – Present · 1 mo

Staff Engineer

Feb 2024 – Apr 2026 · 2 yrs 2 mos

R&D Engineer Sr II

Feb 2023 – Feb 2024 · 1 yr

R&D Engineer Sr I

Promoted

Nov 2019 – Feb 2023 · 3 yrs 3 mos

R&D Engineer II

Jul 2017 – Nov 2019 · 2 yrs 4 mos

  • Worked on Different nodes for SRAM Complier Design
SRAMLayout Design

Realsilicon

2 roles

Senior Design Engineer

Promoted

Jun 2014 – Jul 2017 · 3 yrs 1 mo

  • Worked on Custom SRAM Circuit Design and Layout Design.
Custom SRAM Circuit DesignLayout Design

Design Engineer

Sep 2012 – Jun 2014 · 1 yr 9 mos

  • Worked on Standard Cell Design/Layout, Custom Design/Layout
Standard Cell DesignCustom Design/Layout

Education

BITS Pilani Work Integrated Learning Programmes

Master of Technology - MTech — Microelectronics

Jan 2018 – Jan 2020

Bundelkhand University

Bachelor of Technology - BTech — Electronics & communication

Jan 2008 – Jan 2012

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