AJAY SINGH — Software Engineer
4.5+ year experience in development of Analog & mixed signal IO layout design in TSMC 2nm, 5nm, 7nm & 28nm including GPIO’S, I2C, I3C, BGR, PLL, LVDS, FAIL SAFE , TOLERANT IO’s, SUPPLY CELLS. Expert in EMIR , ESD/PERC, latch up, IR drop & RC delay, self-heating. Expert user of Custom Compiler Design tools , Paragon-X, DRC/LVS/DFM/LDL/PERC. Technology Nodes: TSMC 2nm, TSMC 3nm, TSMC 4nm, TSMC 5nm, TSMC 7nm, TSMC 28nm, GF 22nm. Layout Effects : Electro-migration, ESD/Latch-up, Antenna, WPE, LOD, Crosstalk, IR drop. Layout Techniquies : Matching, Shielding, Guard-ring, Cross talk reduction, STI. A self-motivated person with excellent interpersonal skills and the ability to work in a group efficiently.
Stackforce AI infers this person is a specialist in Analog and Mixed Signal IC design within the semiconductor industry.
Location: New Delhi, Delhi, India
Experience: 6 yrs 5 mos
Skills
- Analog Circuit Design
- Layout Design
Career Highlights
- Over 4.5 years of experience in Analog & mixed signal design.
- Expert in EMIR, ESD, and layout design techniques.
- Proficient in multiple advanced technology nodes.
Work Experience
Synopsys Inc
Senior A&MS layout Design Engineer (2 yrs 5 mos)
A&MS Layout Design Engr, I (2 yrs 1 mo)
Netaji Subhas University of Technology
Teaching Assistant (1 yr 11 mos)
Masters Student (1 yr 11 mos)
Power Grid Corporation of India Limited
Intern (1 mo)
Education
B.tech at Jaypee University of Engineering and Technology
Master of Technology - MTech at Netaji Subhas Institute of Technology
M.Tech at Netaji Subhas Institute of Technology
