Sanjay P — CEO

• 15 years of professional experience in Verilog, RTL design principles, SystemC and TLM for modelling complex digital systems • Expertise in NAND SSD controller architecture and operations • In-depth knowledge of DRAM memory protocols and memory controller architecture • Strong understanding of flash memory technologies and their integration • Hands-on experience with hardware description languages (Verilog) • Familiarity with verification methodologies such as UVM • Hands-on experience with synthesis, place-and-route, and timing closure • Experience with high-performance computing and parallel processing systems • Proficient in C++ programming for system-level modelling • Excellent problem-solving skills and analytical thinking

Stackforce AI infers this person is a VLSI ASIC Engineer with expertise in memory technologies and digital system design.

Location: Bengaluru, Karnataka, India

Experience: 15 yrs 8 mos