Vardan Kirakosyan

CTO

Armenia14 yrs 9 mos experience
Highly Stable

Key Highlights

  • 14+ years in RF and mixed-signal design.
  • Expertise in high-speed PLL and SerDes design.
  • Hands-on experience with cutting-edge FinFET CMOS processes.
Stackforce AI infers this person is a highly skilled Analog/RF Design Engineer with extensive experience in semiconductor design and mixed-signal circuits.

Contact

Skills

Core Skills

Analog Circuit DesignMixed-signal Ic Design

Other Skills

UCIePLLUSB3.0High-Speed SerDesHigh-Speed CircuitryCMOSSimulationsEDAIntegrated Circuit DesignDebuggingVLSIElectronicsVerilog-ADigital Circuit DesignTcl

About

14+ years experience in RF(WiFi), Analog and mixed-signal design in the field of high speed PLLs, SerDes(UCIe,Thunderbolt,USB,PCI,SATA,XAUI) PHY IPs. Summary: Design of analog/mixed-signal circuits, including circuit design/test, layout floor planing, test bench creation, evaluation and debugging. Have an experience of designing different analog and mix signal circuits, such as. • LC tuned buffer 12-15GHz. • LC VCO 12-15GHz(with Momentum) • PFD and CP for 24GHz PLL •Colpitts crystal oscillator. • Adaptive-bandwith PLL. • Oscilators. • Up to 13 GHz clock generator for SerDes Transmitter. • Bandgap voltage references. • Low Dropout Voltage Regulators (LDO). •High-Speed Comparators. •High-Speed transmitters. •Symmetrical, folded cascade etc. OTAs. • High-Speed serializer ADDITIONAL INFORMATION EXPERTISE •Advanced knowledge of MOS transistors and analog circuit design , high speed circuitry design, advanced knowledge of CMOS fabrication processes, basic ESD circuits. •Hands-on experience on IC analog design flow including transistor level design, circuit simulation, test bench creation, static (DC) & timing analysis, frequency, and statistical analysis, noise analysis, capacitance measurement methodology, layout floor-planning & extraction, top level integration, reliability verification, and post-Si debug. •Competent in cutting edge FinFET CMOS process TSMC [16,10,7,2] nm) and 22nm FDSOI. • EM & IR drop analysis on post-layout design. (with Totem) • Self heating analysis. • ESD circuit and layout analysis. EDA Tools • Scripting language->primary knowledge of Perl,Tcl. • Schematic/Layout Editors Virtuoso, Synopsys Custom Designer (SE/LE/SAE(simulation and analysis gui •environment)), Cosmos(SE).• Simulators Spectre, Hspice, FineSim, XA, Hsim.• Verification Mentor Graphics Calibre, Hercules, ICV.• Scopes Saber, CosmosScope, WaveView.

Experience

14 yrs 9 mos
Total Experience
4 yrs 8 mos
Average Tenure
8 mos
Current Experience

Analogue insight™

Principal Analog design engineer

Oct 2025Present · 8 mos · Armenia · Remote

UCIeAnalog Circuit DesignMixed-Signal IC Design

Racyics

Analog & Mixed Signal IC design engineer

Oct 2024Oct 2025 · 1 yr · Dresden, Saxony, Germany · On-site

Adveos

Design Engineer of Microelectronic Circuits

Nov 2018Oct 2024 · 5 yrs 11 mos · Athens, Greece

Synopsys inc

2 roles

Lecturer

Feb 2015Jun 2015 · 4 mos

  • Lecture was dedicated to: Data Converter Fundamentals,DAC and ADC Architectures.

Senior Analog and Mixed Signal R&D engineer at Synopsys

Aug 2011Oct 2018 · 7 yrs 2 mos

  • Hands-on experience on analog part of USB2.0 & USB3.0 products.
  • Co-designed, improved and designed the following circuits from USB2.0 product.
  • <
  • Especially Orientated on PLL and TX (transmiter) parts.
  • Transmitter (TX) part,
  • High/Full/Low speed drivers design.
  • Participated of design High / Full and low speed Transmitters , internal voltage regulators for finfet tsmc16nm/ss10nm technologies. Implementation of customer specific function.
  • Participated design of 960MHz Adaptive-bandwith PLL, for finfet tsmc16nm/ss10nm technologies.
  • Implementation of customer specific function.
  • Strongly participating layout reviews for new technologies such as tsmc16nm and samsung10nm (reliability, devices aging EOL/BOL and EM/IR-Drop analysis)
  • Design shipped to mass production for different PDK with good feedback (results) .
  • >
  • Hands-on experience (porting/designing) on High Speed (5Gb/s | 6Gb/s ) SerDes PHY USB3.0 IP product.
  • <
  • 1.25-3.125GHz Adaptive-bandwith PLL.
  • Phase interpolator circuit.
  • Parallel to serial converter-> serializer circuit.
  • Accurate Duty Cycle Correction (DCC) and I/Q clock correction circuits.
  • Porting of USB3.0 PHY to GF28nm process - 1.25-3.125GHz Adaptive-bandwith PLL, Duty Cycle Correction (DCC) and I/Q clock correction circuits for TX/RX.
  • Design shipped to mass production for different PDK with good feedback (results) .

Education

State Engineering University Of Armenia

Master's degree

Jan 2010Jan 2012

State Engineering University of Armenia

Bachelor's degree — Microelectronics and Semiconductor Devices

Jan 2006Jan 2010

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