Narek Saroyan

Software Engineer

Armenia9 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 7 years of experience in IC design.
Led methodology team driving innovation.
Expertise in Python and Bash scripting for automation.

Stackforce AI infers this person is a semiconductor design expert with a strong focus on integrated circuit development.

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Skills

Core Skills

Integrated Circuits (ic)Research And Development (r&d)

Other Skills

Build & ValidationStandard Cell LibrariesSchematic DesignPhysical DesignPython (Programming Language)EDAObject Oriented ProgrammingDebuggingАлгоритмыShell-скриптингSemiconductorsASICData StructuresCircuit DesignCharacterization

About

Accomplished R&D Engineer with over 7 years of experience in the IC design industry, currently leading a methodology team. Demonstrated leadership in driving innovation and best practices across projects involving advanced technology nodes, including 65nm, 40nm, 28nm, 22nm, 16nm, 14nm, 12nm, 7nm, 5nm, 4nm, 3nm, and 2nm. Highly skilled in IC design and verification, with proven expertise in Python and Bash/Shell scripting to streamline and automate complex workflows. Possesses a strong engineering foundation, holding both bachelor's and master's degrees in integrated circuits.

Experience

9 yrs 2 mos

Total Experience

4 yrs 7 mos

Average Tenure

8 yrs 5 mos

Current Experience

Synopsys inc

3 roles

Research And Development Staff Engineer

Promoted

Nov 2021 – Present · 4 yrs 7 mos

Logic Libraries Department: Build & Validation

Build & ValidationIntegrated Circuits (IC)Research and Development (R&D)

Senior Research And Development Engineer

May 2019 – Oct 2021 · 2 yrs 5 mos

Logic Libraries Department: Build & Validation

Build & ValidationIntegrated Circuits (IC)Research and Development (R&D)

Research And Development Engineer

Dec 2017 – May 2019 · 1 yr 5 mos

Logic Libraries Department: Build & Validation

Build & ValidationIntegrated Circuits (IC)Research and Development (R&D)

Synopsys armenia educational department

Intern(part time) in SAED

Feb 2017 – Nov 2017 · 9 mos · Yerevan

Design of 14nm standard cell library based on GF 14nm technology for educational purpose
Experience in the Design of Standard Cell Libraries including schematic and physical design