Mayank Aggarwal

Product Engineer

Phagwara, Punjab, India6 yrs experience

Key Highlights

Expert in high-speed analog design and mixed-signal ICs.
Led development of advanced SERDES IP at Synopsys.
Strong academic background with research in low power designs.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in analog and mixed-signal IC development.

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Skills

Core Skills

Analog DesignHigh-speed DesignMixed-signal DesignResearchValidation

Other Skills

PCIe7 SERDES IPTSMC 2nm technologyRX AFE blockPPA optimizationHigh-speed analog ICsMixed-signal ICsFinFET technologyRX AFE block designSilicon validationLow power analog front end designTeaching assistanceAnalog circuit designValidation and silicon debugTransceiversSynopsys IC Compiler

About

Open to talk if any interesting analog design job role offering remote position at the same time.

Experience

6 yrs

Total Experience

2 yrs

Average Tenure

1 yr 11 mos

Current Experience

Synopsys inc

3 roles

Analog Design, Sr Staff Engineer

May 2026 – Present · 1 mo

Analog Design, Staff Engineer

Jun 2024 – Apr 2026 · 1 yr 10 mos

☛ Development of PCIe7 SERDES IP running at 128Gbps PAM4 data rate in TSMC 2nm technology.
☛ Led the RX AFE block to deliver optimized design to meet the PPA as per market demand.

PCIe7 SERDES IPTSMC 2nm technologyRX AFE blockPPA optimizationAnalog DesignHigh-Speed Design

Analog Design, Staff Engineer

Sep 2020 – Jun 2024 · 3 yrs 9 mos

☛ Develop high-speed analog and mixed-signal ICs for SerDes IP using the latest FinFET technology
☛ Own the RX AFE block design including ATT, CTLE & VGA to support multiple protocols and channel losses.
☛ Work closely with the System engineers to design AFE to meet JTOL and BER specs.
☛ Work with the silicon validation team in the lab and firmware/rtl designers for silicon bring-up and char.
☛ Own the TX to RX internal/external loopback datapath and supporting debug and characterization in the lab.
☛ Additional experience working on the ADC Interleaver and auxilliary blocks such as signal detector and jtag inside the receiver, common mode hold block inside the transmitter, and RX calibration block.
☛ Assisting in TX DCC and IQ phase calibration

High-speed analog ICsMixed-signal ICsFinFET technologyRX AFE block designSilicon validationAnalog Design+1

University of toronto

Graduate Research Student

Sep 2018 – Sep 2020 · 2 yrs

☛ Supervisor: Prof. David Johns
☛ Thesis: Low power analog front end design (CTLE) for 112 Gbps PAM-4 SERDES receiver
☛ Teaching Assistant for ECE-231 (Introductory Electronics) & ECE-212 (Circuit analysis) courses

Low power analog front end designTeaching assistanceAnalog DesignResearch

Texas instruments

Analog Design Engineer

Jul 2016 – Aug 2018 · 2 yrs 1 mo · Bengaluru, Karnataka, India

☛ Analog circuit design of RS-485 and CAN transceivers in 180nm, 700nm and 1um technology nodes while working in Transceivers & LPAA product lines.
☛ Worked as Analog Validation Engineer for six months in Transceivers product line and did validation and silicon debug of the devices.
☛ Besides this, I have gone through TI`s extensive training program which accelerated my transition into this role.
☛ Relevant Projects :-
> THVD1500 : Designed TX block for low cost, half duplex RS-485 transceiver
> THVD15XX : Designed RX block for high bus fault, surge protected RS-485 transceiver
> Designed TSD, UVLO, IO buffers and Bandgap blocks
> Generic test-board design and developed automation for bench level characterization of devices

Analog circuit designValidation and silicon debugTransceiversAnalog DesignValidation

Tata motors

Summer Intern

May 2015 – Jul 2015 · 2 mos

☛ Mentor: Mr. Santu Hore (Manager, Power Supply, Tata Motors Limited)
☛ Project title: To propose an efficient scheme for load balancing of power transformers and to analyze their efficiency.
☛ Analysed power distribution system and generated SLDs for various substations.
☛ Analysed dynamically changing load curves and recommended modifications to the existing structure.

Isro - indian space research organization

Summer Intern

May 2014 – Jun 2014 · 1 mo · North Eastern Space Applications Centre (NESAC), Shillong

☛ Mentor: Mr. Anjan Debnath (Sci/Engr. at North Eastern Space Applications Centre)
☛ Introduced to the trends of satellite communication with special reference to GPS navigation technology.
☛ Understood atmospheric effects in SATCOM and IRNSS (Indian Regional Navigation Satellite System).