Avinash K. — Product Manager
ASIC Design Lead & Techno-Manager with 20+ years of experience in front-end ASIC/Digital design. Expertise across the full ASIC design flow including microarchitecture, RTL, LINT, CDC/RDC, synthesis, DFT, LEC, and ECO. Proven track record of leading SoC and interface IP subsystem tape-outs and delivering high-quality silicon. Currently Design Lead / Technical Manager at Synopsys India, leading DDR/HBM Interface IP Subsystems Design. Driving architecture definition, customer engagements, and cross-functional execution.
Stackforce AI infers this person is a leader in ASIC and VLSI design with extensive experience in semiconductor technology.
Location: Bengaluru, Karnataka, India
Experience: 23 yrs 4 mos
Career Highlights
- 20+ years in ASIC/Digital design leadership.
- Expertise in full ASIC design flow.
- Proven track record in SoC and IP subsystem tape-outs.
Work Experience
Synopsys Inc
Sr Manager, ASIC Digital Design (1 yr 4 mos)
ASIC Design Manager (3 yrs 9 mos)
Engineer (7 yrs 10 mos)
Altran
Sr ASIC Design Engineer (1 yr)
Intel Corporation
System-on-Chip Design Engineer (1 yr 4 mos)
Agere Systems
Technical Lead (6 yrs 6 mos)
Technical Lead (1 yr 9 mos)
Montalvo Systems
Design Engineer - III (11 mos)
Wipro Technologies
Sr VLSI Design Engineer (4 yrs)
Education
Master of Technology - MTech at Indian Institute of Technology, Madras
Doctor of Philosophy (PhD) at University of Cape Town