Devraj Patil

Software Engineer

India5 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in ASIC Digital Design at Synopsys.
  • Strong foundation in System and Control Engineering.
  • Trained at Siemens, bridging academic and corporate worlds.
Stackforce AI infers this person is a Digital Design Engineer with expertise in ASIC development and embedded systems.

Contact

LinkedIn

Skills

Other Skills

DebuggingVerilogVHDLCMicrosoft ExcelEnglishField-Programmable Gate Arrays (FPGA)Embedded Systems

Experience

5 yrs 11 mos
Total Experience
2 yrs 11 mos
Average Tenure
4 yrs 11 mos
Current Experience

Synopsys inc

2 roles

ASIC Digital Design, Senior Engineer

Promoted

Jan 2024 – Present · 2 yrs 5 mos

ASIC Digital Design, Engineer II

Jun 2021 – Dec 2023 · 2 yrs 6 mos

Siemens

Graduate Trainer Engineer

Jul 2017 – Jul 2018 · 1 yr

  • New Start for New Life - College to Corporate

Education

Indian Institute of Technology, Roorkee

MTech - Master of Technology — System and Control Engineering

Jan 2019 – Jan 2021

Karlsruhe Institute of Technology (KIT)

M.Tech — Advanced Digital System Design

Jan 2020 – Jan 2021

COEP Technological University

Bachelor of Technology (B.Tech.) — Electrical Engineering

Jan 2013 – Jan 2017

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