Cedric Alquier

Product Engineer

Rouen, Normandy, France25 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 23 years of experience in hardware verification.
Expert in architecturing hardware-assisted verification solutions.
Published article in DesignCon 2003 on co-simulation techniques.

Stackforce AI infers this person is a Hardware Verification Expert in the EDA industry.

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Skills

Core Skills

Hardware VerificationDebuggingSoftware DevelopmentTechnical Analysis

Other Skills

Performance analysisSimulationEmulationCoordinationProduct qualityCustomer supportHW/SW project developmentDebug database developmentSoftware interface developmentCompilation flow developmentDatabase developmentSystemCHDL simulatorsTechnical expertiseFailure analysis

About

As a Scientist at Synopsys Inc with over 23 years of experience, I focus on Architecturing Hardware Assisted Verification. My expertise spans Debugging complex problems, performance analysis, architecturing and developing innovative solutions, in an international environment. My work integrates a deep understanding of hardware verification, simulation, emulation, clocking and debug. Dedicated to advancing technology through collaboration and innovation, I remain committed to delivering high-quality solutions that meet complex industry needs.

Experience

25 yrs 5 mos

Total Experience

12 yrs 9 mos

Average Tenure

13 yrs 9 mos

Current Experience

Synopsys inc

3 roles

Scientist

Sep 2020 – Present · 5 yrs 9 mos

DebuggingPerformance analysisHardware verificationSimulationEmulation

Principal Engineer

Jun 2015 – Aug 2022 · 7 yrs 2 mos

Staff R&D engineer

Sep 2012 – Aug 2022 · 9 yrs 11 mos

Emulation and verification engineering (eve)

R&D Engineer

Jan 2001 – Oct 2012 · 11 yrs 9 mos

EVE is a successfull EDA startup specialized in IC verification and debug products, especially hardware emulators.
I'm currently in charge of:
Coordination of USA/France R&D
Participation to product quality and direct customer support.
Developement of various HW/SW projects
In the past:
Responsible of debug database development
Developement of software interfaces with HDL simulators, systemC, C/C++.
Developpments compilation flow dev. and more specifically memory flow.
Publication of an article in DesignCon 2003: "Co-Simulation Between SystemC and a New Generation Emulator"
I'm mostly working with:
O.S: Linux, UNIX.
Software: C++, C, STL, Perl, TCL/TK, Lex & Yacc, purify/quantify, UML, CVS
Hardware: Verilog, VHDL, EDIF, SystemC, FPGAs/ICs/µP Architectures
EDA: HDL simulators (VCS, NCSIM, Modelsim), PLI/VPI/VHPI, Zebu Emulators, RTL synthesis, Xilinx compilation flow