Shubham Yadav — Software Engineer
Verification Engineer with 7+ years of experience at Synopsys in Design Verification, VIP development, and automation. Skilled in UVM, SystemVerilog, and serial communication protocols including UALink, Ethernet, CAN and SPI. Currently pursuing M.Tech in Data Science and Business Analytics at IISc Bangalore. Passionate about automation, problem solving, and building efficient verification solutions.
Stackforce AI infers this person is a Verification Engineer with a strong focus on automation and functional verification in the semiconductor industry.
Location: Noida, Uttar Pradesh, India
Experience: 6 yrs 4 mos
Skills
- Functional Verification
- Design
Career Highlights
- 7+ years of experience in Design Verification.
- Expertise in UVM and SystemVerilog.
- Currently pursuing M.Tech in Data Science.
Work Experience
Synopsys Inc
R&D Engineer, Staff (2 yrs 4 mos)
R&D Engineer, Sr I (7 mos)
R&D Engineer, II (1 yr 11 mos)
R&D Engineer, I (1 yr 6 mos)
Intern (Technical-Engineering) (6 mos)
Intern (Technical-Engineering) (9 mos)
Directorate of Coordination Police Wireless
Summer Internship (0 mo)
Education
M.Tech at Indian Institute of Science (IISc)
B.Tech. at National Institute of Technology Delhi