SOURABH MALPANI

CTO

Bengaluru, Karnataka, India9 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Led architecture design for Qualcomm's Snapdragon chipsets.
Enhanced performance and power efficiency for next-gen chipsets.
Expert in SoC performance analysis across multiple stages.

Stackforce AI infers this person is a Semiconductor and Automotive expert with a focus on SoC architecture and performance.

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Skills

Core Skills

Soc ArchitectureSystem PerformanceSystems Engineering Process

Other Skills

Performance ModellingTLMSystemCAutomotive SimulationPerformance AnalysisCC++Microsoft OfficeHTMLMatlabSystem C

About

• Involved in the architecture design and development of Qualcomm's Snapdragon chipsets, significantly enhancing the performance and power efficiency of next-generation chipsets used in Smartphones, AR-Smart Glass, and IoT products. Our contributions directly impact the overall product performance, ensuring superior user experiences and competitive advantages in the market • Lead the architecture and performance analysis of SoCs during Pre-Silicon simulation, Pre-Silicon emulation, and Post-Silicon stages, collaborating closely with cross-functional teams to ensure optimal performance and successful project outcomes

Experience

9 yrs 6 mos

Total Experience

4 yrs 9 mos

Average Tenure

8 yrs 11 mos

Current Experience

Qualcomm

3 roles

Lead Engineer Sr, SoC Performance and Architecture

Promoted

Jul 2022 – Present · 3 yrs 11 mos · India

Lead Architecture and Performance Analysis of SoCs at Pre-Silicon Simulation, Emulation and Post-Silicon with the following activities:
System performance and architectural analysis, SoC Architecture Exploration, Performance Modelling using TLM and SystemC.
Perform detailed analysis of the existing software to provide innovative recommendations to improve performance and memory utilization, including software optimizations, SW/HW partitioning, cache/TCM sizing, etc.
System issue Debug, identify workable solution for system issues including HW/SW optimizations to be fed back to Arch/design/SW teams.
Responsible for end-to-end Pre-Silicon Performance Analysis, Analyze and Identify performance bottlenecks in SoCs for various use cases, Devise mitigation plans for existing performance limitations.
Responsible for defining use-case scenarios aligning to product requirement, enabling, and validating the use-case performance on system.
Pre-Silicon vs Post-Silicon Usecase correlation activities across core IP owners, Emulation, and Silicon Reference Platforms.

SoC ArchitectureSystem Performance