Vishal Rathee

Software Engineer

Noida, Uttar Pradesh, India6 yrs experience

Most Likely To SwitchAI Enabled

Key Highlights

Expert in AI Accelerator chip verification.
Proven track record in 5G IP verification.
Strong background in UVM and SystemVerilog.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in AI and 5G technologies.

Contact

vishaliit2016@gmail.com LinkedIn

Skills

Core Skills

Artificial Intelligence (ai)System On A Chip (soc)Universal Verification Methodology (uvm)Performance VerificationSystemverilogFunctional VerificationVerification And Validation (v&v)UvmVerilog

Other Skills

VCSQuestaSimDigital ElectronicsAssertion Based VerificationFormal VerificationEmulationObject-Oriented Programming (OOP)DebuggingGitC++C (Programming Language)Static Timing AnalysisLeadershipPublic SpeakingPalladium

About

Experienced Design and Verification Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Verilog/SystemVerilog, UVM, Assertion, Coverage, Python.

Experience

6 yrs

Total Experience

1 yr 6 mos

Average Tenure

1 yr 11 mos

Current Experience

Microsoft

2 roles

Senior Design Verification Engineer

Promoted

Mar 2026 – Present · 3 mos · Noida, Uttar Pradesh, India

Working on development and verification of Microsoft's AI Accelerator chip #Maia

Artificial Intelligence (AI)System on a Chip (SoC)

Design Verification Engineer 2

Jul 2024 – Mar 2026 · 1 yr 8 mos · Noida, Uttar Pradesh, India

Universal Verification Methodology (UVM)Performance Verification

Intel corporation

2 roles

Senior Verification Engineer

Promoted

Oct 2023 – Jul 2024 · 9 mos · Bengaluru, Karnataka, India · Hybrid

▪ Worked on Verification of RF Transceiver IP. Responsible for complete sign-off starting from testplan to coverage closure.
▪ Developed UVM testbench from scratch to verify DRF IP and contributed to every block - Driver, Monitor, Scoreboard, Testcases, Integration, Functional Coverage, Assertions

Universal Verification Methodology (UVM)SystemVerilog

Verification Engineer 2

Aug 2021 – Sep 2023 · 2 yrs 1 mo · Bengaluru, Karnataka, India · Hybrid

▪ Successfully completed verification of different 5G IPs (LDPC, Polar, TURBOV)
Hands on experience on both Coverage based and Assertion based verification.
▪ Submitted a total of 6 IDFs (Invention Disclosure Form)

Functional VerificationVCS

Synopsys inc

Verification Engineer

Sep 2020 – Aug 2021 · 11 mos · Bengaluru, Karnataka, India

Functional spec reviews, defining validation test plan, RTL/test case creation, checkers, test running, regression, triage and bug reporting for the developed features.
Review and Co-ordination with R&D, PE to identify customer use models required to be validated and work on open critical Jira’s to meet the quality expectations of the customers.

Verification and Validation (V&V)VCS

Cadence design systems

DV Engineer

May 2020 – Sep 2020 · 4 mos · Noida, Uttar Pradesh, India

Verification of PCIe DUT with Cadence Accelerated VIP into IXCOM/ICE mode of Palladium platform
Successful Bring up of PCIe B2B on palladium.
Connected the PCIe as RC and AVIP as EP and successfully linked up till Gen5.

UVMSystemVerilog