Navinkumar W

Product Engineer

Chennai, Tamil Nadu, India5 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 5 years of experience in VLSI domain.
  • Expertise in RTL design and ASIC verification.
  • Proficient in multiple programming languages and verification tools.
Stackforce AI infers this person is a VLSI Engineer with expertise in hardware design and verification for the healthcare industry.

Contact

Skills

Core Skills

Rtl Design With Verilog/systemverilogAsic Verification With Systemverilog/uvm

Other Skills

Formal Verification - DVLogic SynthesisVerilogSystemVerilogFPGA Board Bring-UpPost Silicon Validationcomputer organization and architectureVLSICDC/Lint - RTL Quality ChecksFPGA Board Testing/DebuggingPython / TCL ScriptingC/C++x86 AssemblyVLSI Signal IntegrityClock Tree Synthesis

About

Finished Masters degree in VLSI and having 5 years of experience in VLSI Domain. Worked on RTL design, synthesis, debugging, and verification of ASIC & FPGA designs. Having good communication skills, willing to learn & adapt to new technologies. Skills: -> Verilog, SystemVerilog and VHDL -> C, C++ and Python. -> Assertions, Coverage and UVM -> RTL Quality Checks - CDC/Lint, Static Property checking. -> Worked on Post Silicon Validation, FPGA Board Bring-Up and debugging. -> Protocols: SPI, QSPI, UART, I2C, Ethernet, DDR3. APB, AXI Tools :- VCS, Verdi, Xcelium, QuestaSim, Genus, JasperGold, Spyglass. Vivado, Vitis SDK and MS Visual Studio. FPGA’s :- Kintex-7, Zynq-7000, and Artix-7. Experience: Started the career at NIELIT Calicut, Kerala, as VLSI Project Staff from September 2020. Here worked on an FPGA & ASIC based Ultrasound Imaging Hardware design project under SMDP-C2SD funded by MietY (Govt). Joined L&T Technology services on January 2022 as VLSI Engineer. Worked at multiple projects on RTL Design, Quality checks, Static property checking and UVM/C testbench. Joined Hitachi Energy in June 2023 and Currently working as a R&D Engineer on HVDC system.

Experience

5 yrs 7 mos
Total Experience
1 yr 10 mos
Average Tenure
3 yrs
Current Experience

Hitachi energy

Research And Development Engineer

Jun 2023Present · 3 yrs · Chennai · Hybrid

L&t technology services limited

VLSI Engineer

Jan 2022May 2023 · 1 yr 4 mos · Mysore, Karnataka, India

Formal Verification - DVLogic SynthesisRTL Design with Verilog/SystemverilogASIC Verification with Systemverilog/UVM

Nielit calicut

Project Associate (VLSI Group)

Sep 2020Dec 2021 · 1 yr 3 mos · Kozhikode, Kerala, India · On-site

Logic SynthesisRTL Design with Verilog/Systemverilog

Education

NATIONAL INSTITUTE OF ELECTRONICS & INFORMATION TECHNOLOGY (NIELIT)

PG Diploma — VLSI

Aug 2019Feb 2020

Dr.SIVANTHI ADITANAR COLLEGE OF ENGINEERING

Master of Engineering - MEng — VLSI Design

Jul 2015Jun 2017

Infant Jesus College of Engineering and Technology

Bachelor of Engineering - BE

Jun 2011May 2015