Subhiksha J — Software Engineer
* Have 3+ years experience as an AMS Layout Design Engineer. * Having good experience in different node like TSMC 5nm, TSMC 3nm, TSMC 2nm, SS5 *Strong exposure in Analog matching techniques, elimination of latch-up, shielding, area. * Good experience in QA checks, EM, IR fixes
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Analog Layout and Quality Assurance.
Location: Bangalore Urban, Karnataka, India
Experience: 2 yrs 10 mos
Skills
- Analog Layout
- Layout Design
Career Highlights
- 3+ years as AMS Layout Design Engineer.
- Expertise in TSMC 5nm, 3nm, and 2nm nodes.
- Strong in Analog matching techniques and QA checks.
Work Experience
Synopsys Inc
A&MS Layout Design Senior Engineer (1 yr 4 mos)
A&MS Layout Design Engineer1 (1 yr 6 mos)
A&MS layout Intern (9 mos)
Epitome Circuits
Student Trainee (11 mos)
Education
Master of Technology at Birla Institute of Technology And Science (BITS), Pilani
Bachelor of Engineering - BE at RNS Institute of Technology - India
