Aakash Gupta

Software Engineer

Greater Delhi, India4 yrs 3 mos experience

Most Likely To Switch

Key Highlights

Expert in Logic Synthesis and Timing Closure for advanced SoC designs.
Resolved over 600 critical design issues in high-stakes environments.
Strong collaboration with R&D teams to enhance design tools.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Logic Synthesis and Verification.

Contact

aakashguptaak07@gmail.com LinkedIn

Skills

Core Skills

Logic SynthesisFormal Equivalence Verification

Other Skills

RTL DesignRTL CodingVerilogSystemVerilogSynopsys Design CompilerSynopsys Fusion CompilerSynopsys FormalityFront-End DesignStatic Timing AnalysisScriptingLinuxSynopsys PrimetimeUnified Power Format (UPF)Back-End DesignProblem Solving

About

Senior Engineer at Synopsys specializing in Design Implementation and Timing Closure for cutting-edge SoC designs. Currently part of the Customer Success Group (CSG), I provide specialized technical expertise and design enablement for AMD, Cisco, and Marvell, ensuring successful tape-outs on advanced process nodes (N3, N5, N6). My expertise lies at the intersection of Logic Synthesis, Static Timing Analysis (STA), and Formal Equivalence Verification (FEV). I have a proven track record of resolving complex design bottlenecks, having successfully closed over 600+ critical design issues involving Fusion Compiler, PrimeTime, and Formality. Core Expertise: ⚡ Logic Synthesis & STA: Expert in FC-FE/BE flows, optimizing timing QoR, and resolving timing related challenges on sub-7nm nodes. 🛡️ Formal Verification: Specialist in resolving Formality hard verifications, SVF/DPX inconsistencies, and runtime reduction. 🔋 Low Power: Hands-on experience in MV-UPF flow and resolving complex power-aware design issues. 🤝 R&D Collaboration: I work directly with Synopsys RnD teams to drive feature enhancements and root-cause tool bugs, ensuring the toolset meets the demands of next-gen silicon. Always interested in discussing the latest trends in RTL-to-GDSII flows, timing closure strategies, and advanced node challenges.

Experience

4 yrs 3 mos

Total Experience

1 yr 5 mos

Average Tenure

2 yrs 11 mos

Current Experience

Synopsys inc

Senior Engineer

Jul 2023 – Present · 2 yrs 11 mos · Hyderabad · On-site

Part of CSG (Customer Success Group) team and dedicatedly working with AMD Design/CAD teams to resolve critical flow/design and
tape-out issues.
Working closely with RnD teams to design and implement feature enhancements and resolve tool bugs.
Hands-on experience in resolving issues of Synthesis, Formal Equivalence Verification, MV-UPF, timing QoR. Extensive experience in
resolving Formality issues.
Expertise in failing points debug, Runtime reduction, resolving FM hard verification, DPX and SVF inconsistency issues.
Ensuring that the flow works smoothly across different designs and different tech nodes.
Hands-on experience on the complete FC-FE flow & good understanding on the FC-BE flow.
Resolved more than 600 complex design issues spanning FC, MV-UPF, DC/DC-NXT, RLTA, FM.
Collaborated with CAD teams & designers from Cisco and Marvell to support Design compiler, Fusion complier & Formality tools.

RTL DesignRTL CodingVerilogSystemVerilogSynopsys Design CompilerSynopsys Fusion Compiler+10

Texas instruments

Analog Field Application Engineer

Jan 2023 – Jun 2023 · 5 mos · India · On-site

• Developed practical expertise in PMICs (LDOs, Buck/Boost Converters) by analysing datasheets and assisting in schematic reviews, applying this knowledge to support customer design-in activities and technical issue resolution, which aided in 2 successful product evaluations.