Afonso Oliveira

Software Engineer

Portugal2 yrs 3 mos experience

AI EnabledAI ML Practitioner

Key Highlights

Pioneered RISC-V Unified Database growth from prototype to global standard.
Expert in hypervisor-level performance isolation for embedded AI systems.
Influences hardware architects for optimal software solutions.

Stackforce AI infers this person is a Software Engineer specializing in RISC-V architectures and embedded systems.

Contact

Skills

Core Skills

Risc-v Software DevelopmentDatabase ManagementMachine LearningEmbedded SystemsEmbedded Ai SystemsHypervisor Development

Other Skills

RISC-V Unified DatabaseGolangLLVMGCCLLM QuantizationZephyr RTOSAutomationToolingBenchmarkingHypervisorsTinyMLTensorFlowMemory SystemsBashCompilers

About

Building the future of RISC-V software, one upstream at a time. I develop Sofware support for RISC-V architectures. Currently, I work on the et-platform and previously I worked on Synopsys ARC-V CPUs. I was one of the initial contributors of the RISC-V Unified Database, scaling it from prototype to global standard. Previously, I researched hypervisor-level performance isolation for embedded AI systems. I also try my best to influence architects and HW engineers to do the right thing, so I don't have to write tricky software hacks.

Experience

2 yrs 3 mos

Total Experience

1 yr 3 mos

Average Tenure

3 mos

Current Experience

Ainekko

Software Engineer

Feb 2026 – Present · 3 mos · Porto, Portugal · Remote

Synopsys inc

2 roles

Senior Software Engineer

Sep 2024 – Feb 2026 · 1 yr 5 mos · Hybrid

RISC-V Unified Database (UDB)
Grew UDB from 0 → 100+ GitHub stars and 1 → 30+ external contributors.
Presented work at FOSDEM and multiple RISC-V Summits.
Cross-Verification Framework for validating Golang, LLVM, and GCC against UDB definitions.
LLM Quantization Research
Replicated AWQ, SmoothQuant, SpinQuant & GPTQ for real-world deployments.
Produced benchmarks and internal reports guiding NPU model deployment.
Zephyr RTOS Contributions
Upstreamed ARC-V RMX/RHX CPU definitions and architecture support.
Implemented AIA and SMRNMI; achieved full build/boot/test success on HW & emulators.
Automation & Tooling
Built reproducible benchmarking and regression pipelines for ML evaluation.
Developed automated docs & workflow systems boosting productivity across teams.

RISC-V Unified DatabaseGolangLLVMGCCLLM QuantizationZephyr RTOS+4

Summer Bootcamp

Jul 2024 – Sep 2024 · 2 mos · Hybrid

Created Gap Analysis between RISC-V ISA Manual and concorrents.
Join Unified Database as 2nd contributor and pushed into further RVI adoption (Last checked it's on 50+ contributors)
Automated Documentation buildm for 1000+ instructions
10+ changes on upstream RISC-V official repositories, such as the riscv-isa-manual and riscv-opcodes

Centro algoritmi

Student Researcher

Feb 2024 – May 2025 · 1 yr 3 mos

Driving cutting-edge research in memory systems, hypervisors and embedded AI at Centro Algoritmi, where I:
Architect hypervisor-level QoS by engineering a memory bandwidth reservation mechanism on the Bao hypervisor—dramatically boosting system performance under contention
Leverage TinyML to optimize dynamic memory allocation, cutting performance degradation on critical cores by 80% while preserving 90% throughput on non-critical cores
Build platform-agnostic ML benchmarks to rigorously stress memory hierarchies across diverse architectures
Automate testing pipelines, creating a benchmarking framework that slashes manual effort by 90%
Design micro-benchmarks for precise, low-level memory hierarchy throughput analysis
Disseminate findings at top peer-reviewed venues, including:
IA&AI: Interference Analysis in Multi-core Embedded AI Systems (Springer)
H-MBR: Hypervisor-level Memory Bandwidth Reservation (Dagstuhl)
SP-IMPact: Framework for Static Partitioning Interference Mitigation (Dagstuhl) (Co-authored)
Technologies & Tools: C • Python • TinyML • TensorFlow • TFLite • ARMv8 • RISC-V • Hypervisors • Git • Docker • Xilinx UltraScale+