Akash Bidarera Nagesh

Software Engineer

San Diego, California, United States4 yrs 2 mos experience

Key Highlights

Expert in FPGA and ASIC design.
Developed automation tools at Infoblox.
Master's student focused on cutting-edge hardware architecture.

Stackforce AI infers this person is a skilled engineer in hardware design and software automation within the tech industry.

Contact

Skills

Core Skills

Field-programmable Gate Arrays (fpga)Java

Other Skills

Xilinx VivadoVerilogC++Application-Specific Integrated Circuits (ASIC)Digital DesignPython (Programming Language)VHDLSystemVerilogC (Programming Language)QuestaSimLiberoLinuxMatlabSeleniumTest Automation

About

I’m a Master’s student in Computer Engineering at USC, focused on Computer Architecture, digital design, VLSI, and hardware accelerators. With experience in FPGA control systems and ASIC design, I’ve worked on high-speed I/O and multi-core processors. Previously, at Infoblox, I developed automation tools and optimized processes using APIs

Experience

4 yrs 2 mos

Total Experience

1 yr 7 mos

Average Tenure

11 mos

Current Experience

Apple

Cellular SoC Firmware Engineer

Jul 2025 – Present · 11 mos · San Diego, California, United States

Usc information sciences institute

Digital Design Engineer - ASIC & FPGA

Sep 2024 – Dec 2024 · 3 mos · Arlington, Virginia, United States · Remote

Xilinx VivadoField-Programmable Gate Arrays (FPGA)

University of southern california

Directed Research - WiDeS Lab

Mar 2024 – Jul 2025 · 1 yr 4 mos · Los Angeles, California, United States · Hybrid

Design a control system on Intel MAX-10 FPGA, ensuring precise timing and signal synchronization between transmitter and receiver. Resolve a race condition in the MIMO transmitter design, and improving system stability across all clock domains. Implement a trigger-based initialization system for a waveform generator, achieving 0.1-microsecond timing precision

Xilinx VivadoField-Programmable Gate Arrays (FPGA)

Infoblox

3 roles

Software Engineer I

Oct 2022 – Aug 2023 · 10 mos

Java

Software Engineer

Aug 2021 – Oct 2022 · 1 yr 2 mos

Java

Software Engineer Intern

Jan 2021 – Jul 2021 · 6 mos

Java

Centre for research in space science and technology, pesu

Intern

Jun 2019 – Sep 2020 · 1 yr 3 mos · Bengaluru, Karnataka, India

Executed implementation of Viterbi algorithm with added functionalities, decoding a continuous stream of satellite data on the Zynq-7000
The design block functions seamlessly for any constraint length and skillfully corrects up to 5 out of 35 bit errors, ensuring robust data integrity
Executed thorough integration tests with DRDO’s Sindhu Nethra Satellite, precisely analyzing telemetry data. Resolved complex system issues, achieving integration and enhancing satellite performance with a 95% data accuracy rate

Xilinx VivadoField-Programmable Gate Arrays (FPGA)