Aman Agarwal — Software Engineer
Experienced Design Automation Engineer with 8+ years with strong work ethic and substantial customer-oriented Industrial experience. Hand on experience in PDK QA and development compatible with custom compiler Responsible for pcell development, layout creation, parameter callbacks, simulation, netlist enablement, symbol creation, techfile, release notes compatible with custom compiler. Hands on experience in layout automation using Cadence skill and python for analog and mixed signal design. Developed methodology for DRC runsets QA for various foundries Documentation of PDK release and automation flows to support global teams. Scripting language: Tcl,Python, Perl ,Shell, awk and Cadence Skill. Tools: Revision control system (Perforce), Cadence virtuoso platform, Custom Compiler
Stackforce AI infers this person is a Design Automation Engineer with expertise in semiconductor design and automation technologies.
Location: Hyderabad, Telangana, India
Experience: 9 yrs 8 mos
Skills
- Design Automation
- Problem Solving
- Scripting
- Version Control
- Communication
Career Highlights
- 8+ years of experience in design automation.
- Expert in PDK QA and development.
- Proficient in multiple scripting languages.
Work Experience
Synopsys Inc
Staff Engineer (2 yrs 4 mos)
Senior Solution Engineer (2 yrs 10 mos)
Micron Technology
CAD Engineer (3 yrs 2 mos)
Sankalp Semiconductor
Senior Design Engineer (2 yrs 1 mo)
Synopsys Inc
Technical Intern in Synopsys (1 yr)
Cognizant
.NET Developer (7 mos)
Education
Master of Technology (MTech) at VIT University
Bachelor of Engineering (BE) at Sri Shankracharya College of Engineering And Technology
class 12th at Sir Shankara Vidyalya
