Amrutha Murali

Software Engineer

Ernakulam, Kerala, India9 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

7 years of experience in RTL and Logic Synthesis.
Expertise in Static Timing Analysis and VLSI design.
Led multiple smartphone processor projects successfully.

Stackforce AI infers this person is a Semiconductor and Embedded Systems expert with strong RTL and VLSI design capabilities.

Contact

Skills

Core Skills

Logic SynthesisStatic Timing Analysis

Other Skills

VerilogPLDRCCDCLECTMAXVery-Large-Scale Integration (VLSI)VerdiClearCaseDFTSDCUPFRTL DesignRTL CodingRISC-VCadence Virtuoso

About

Up-skilling in RTL and microarchitecture currently. 7 years of experience in RTL, Logic Synthesis and the quality checks like LEC, Pre-STA, TMax, CLP, etc.

Experience

9 yrs

Total Experience

3 yrs

Average Tenure

4 yrs 7 mos

Current Experience

Qualcomm

2 roles

Senior Lead Engineer

Promoted

Dec 2023 – Present · 2 yrs 6 mos · Bengaluru, Karnataka, India · Hybrid

Senior Engineer

Nov 2021 – Dec 2023 · 2 yrs 1 mo · Bengaluru, Karnataka, India · Hybrid

FE Design Engineer

VerilogPLDRCCDCLogic SynthesisLECStatic Timing Analysis+4

Mediatek

Senior Engineer

Jul 2018 – Nov 2021 · 3 yrs 4 mos · Karnataka, India

VLSI Engineer specialized in Logic Synthesis.
Has exposure to STA as well.
Worked on 7 smartphone processor projects, with good amount of co-work with RTL design and Physical Design teams.
Able to take up block designs through synthesis, ensuring best possible PPA, while maintaining the netlist quality in all aspects.
Domains: Logic Synthesis, STA, SDC, TMax, LEC, CCD, CTSSanity, ERC, CLP, UPF, Basic Understanding of RTL, DFT, PD..

Logic SynthesisStatic Timing AnalysisLECTMaxDFTSDC+1

Ignitarium technology solutions pvt ltd

Intern

Jun 2017 – May 2018 · 11 mos · India

Worked on the project "Virtual Reality Interface on FPGA" for a leading American Company.
Was able to work on a Submodule design architecture and its RTL code creation.
Was a part of taking the entire project design's RTL through synthesis and physical design flows to custom board level implementation, with optimum PPA.
Took part in application software coding to enable the functionality of the hardware design.