Anandu Narayanan

Software Engineer

Tiruvalla, Kerala, India6 yrs 10 mos experience
Highly Stable

Key Highlights

  • 3+ years in RTL verification across multiple projects.
  • Expertise in UVM and formal verification tools.
  • Strong background in digital circuit design and programming.
Stackforce AI infers this person is a skilled RTL verification engineer with a focus on digital design and formal verification.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)

Other Skills

Formal VerificationSystemVerilogComputer ArchitectureTest PlanningTestbench ArchitecturePython (Programming Language)Digital Circuit DesignDigital ElectronicsVerilogPythonLinuxC (Programming Language)C++Functional VerificationObject-Oriented Programming (OOP)

About

3+ years of experience in rtl verification. Worked across multiple verification projects from IP level to Subsystem level. Experience in formal tools and development of formal testbench for design verification.

Experience

6 yrs 10 mos
Total Experience
2 yrs 5 mos
Average Tenure
1 yr 11 mos
Current Experience

Nvidia

Senior Verification Engineer

Jul 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India

Qualcomm

2 roles

Senior Engineer

Promoted

Nov 2022 – Jul 2024 · 1 yr 8 mos · Bangalore Urban, Karnataka, India

Universal Verification Methodology (UVM)Formal Verification

Engineer

Apr 2021 – Nov 2022 · 1 yr 7 mos · Bangalore Urban, Karnataka, India

Universal Verification Methodology (UVM)SystemVerilog

Smart iops

Member Of Technical Staff

Aug 2019 – Apr 2021 · 1 yr 8 mos · Thiruvananthapuram Area, India

Universal Verification Methodology (UVM)SystemVerilog

Quest global

Intern

May 2018 – Jun 2018 · 1 mo · Trivandrum

Education

College of Engineering Trivandrum

Bachelor of Technology

Jan 2015 – Jan 2019

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