Anish Krishnakumar

CEO

Bengaluru, Karnataka, India12 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in microarchitecture and power estimation.
Proven experience in physical design for advanced process nodes.
Strong background in FPGA prototyping and emulation.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in microarchitecture and physical design.

Contact

Skills

Core Skills

MicroarchitecturePower EstimationPhysical DesignStatic Timing Analysis

Other Skills

RTL designGate level simulationsFPGA prototypingNetlist to GDSII implementationLeakage AnalysisSemiconductorsFPGAEmbedded SystemsLinuxASICCC++VerilogVHDLPerl

About

I am a CPU power analysis engineer at Arm. Prior to this, I pursued my Ph.D at University of Wisconsin-Madison advised by Prof. Umit Ogras and looked into interesting research problems in Heterogeneous SoC architectures. My prior experience was with Microarchitecture Research Lab (MRL), Intel Bangalore where I worked on multiple aspects of the design flow such as microarchitecture, design, verification, gate level simulation, net list based power estimation and FPGA based emulation of an IP. Prior to my stint at Intel, I worked at Qualcomm Bangalore for about 2.5 years on Physical Design where I worked on aspects of the backend flow for testchips in advanced process nodes.

Experience

12 yrs 5 mos

Total Experience

2 yrs 5 mos

Average Tenure

3 yrs 3 mos

Current Experience

Arm

3 roles

Principal Engineer

Promoted

Apr 2026 – Present · 2 mos

Staff Engineer

Jul 2025 – Mar 2026 · 8 mos

Staff Engineer

Jan 2023 – Jun 2025 · 2 yrs 5 mos

University of wisconsin-madison

Graduate Research Assistant

Aug 2020 – Dec 2022 · 2 yrs 4 mos · Madison, Wisconsin, United States

Arizona state university

Graduate Research Associate

Aug 2018 – Aug 2020 · 2 yrs

Intel corporation

Research Scientist

Oct 2015 – May 2018 · 2 yrs 7 mos · Bangalore

Involved in the microarchitecture and RTL design of blocks in a hardware accelerator IP for computer vision
Focussed on the following at IP top level:
Integration of all modules at top level and validation
Testbench infrastructure development and maintenance
Gate level simulations for verification and for collateral generation for power estimation
Netlist based power estimation using Synopsys PrimeTime PX
Emulation and prototyping of the IP on Altera FPGA
Involved in microarchitecture and power improvements of an Intel SoC

MicroarchitectureRTL designGate level simulationsPower estimationFPGA prototyping

Qualcomm

3 roles

Engineer

Promoted

May 2015 – Sep 2015 · 4 mos · Bengaluru Area, India

Involved in the following tasks on 10nm/14nm/16nm/20nm process nodes:
Netlist to GDSII implementation at block level involving Floorplan, Clock Tree Synthesis, Placement and Routing (PnR), Static Timing Analysis/Timing Closure and Physical Verification (DRC/LVS/ERC) Closure
Leakage Analysis
Library Generation
Reference Flow
IR Analysis
Methodology to achieve high utilization in advanced technology nodes
Robust clock network methodology for skew minimization for better timing convergence

Physical DesignNetlist to GDSII implementationStatic Timing AnalysisLeakage Analysis