Apoorva Mathur

Director of Engineering

Delhi, India31 yrs 9 mos experience

Highly Stable

Key Highlights

Director R&D with extensive experience in semiconductor verification.
Expert in managing cross-functional teams for product development.
Proven track record in delivering complex verification IPs.

Stackforce AI infers this person is a semiconductor industry expert with strong leadership in R&D and verification management.

Contact

Skills

Core Skills

Functional VerificationVerification Ip ManagementProduct DevelopmentEngineering Management

Other Skills

AHBAMBA AHBASICAssertion IPsAutomotiveAutomotive ElectronicsC++CadenceCross-functional Team ManagementDebuggingEDAEmbedded SystemsEmployee Learning & DevelopmentFPGAFormal Verification

About

Director R&D at Siemens EDA.

Experience

31 yrs 9 mos

Total Experience

7 yrs 4 mos

Average Tenure

2 yrs 2 mos

Current Experience

Siemens eda (siemens digital industries software)

Director R&D

Apr 2024 – Present · 2 yrs 2 mos · India · On-site

Synopsys inc

2 roles

Director R&D

Promoted

Sep 2016 – Apr 2024 · 7 yrs 7 mos · Noida Area, India

Sr. Engineering Manager, Verification IP

Oct 2011 – Sep 2016 · 4 yrs 11 mos · Noida Area, India

Responsible for management and delivery of Native SystemVerilog based, UVM/OVM/VMM compliant Verification IPs for MIPI and HDMI

Functional VerificationVerification IP Management

Cadence design systems

3 roles

Senior Engineering Manager

Aug 2010 – Oct 2011 · 1 yr 2 mos · Noida Area, India

Rapid Prototyping Platform
Managed the cross functional team responsible for development, product validation and evaluations.

Senior Engineering Manager

Promoted

Jul 2004 – Sep 2010 · 6 yrs 2 mos · Noida Area, India

Verification IP Management and development.
SystemC/'e' based Verification IPs
Assertion IPs for formal verification, simulation and acceleration
Transaction Based Acceleration VIPs

Engineering Manager

Feb 2002 – Jun 2004 · 2 yrs 4 mos · Noida Area, India

Verification IP Management and Development
TestBuilder/SystemC based Verification IPs

Tality corporation

Lead Design Engineer

Nov 2000 – Feb 2002 · 1 yr 3 mos · Noida Area, India

Front End Design and Verification
Block level place and route

Cadence design systems

2 roles

Lead Application Engineer

Jun 1999 – Oct 2000 · 1 yr 4 mos

Supported customers based in India and Asic-pac for the complete portfolio of Cadence products and services.
System level (SPW)
Board design (Allegro)
Functional verification (Verilog-Xl/IUS)
Synthesis (Ambit)
Place & Route (Silicon Ensemble)
Custom IC