Ashish Dahare

Software Engineer

Bilaspur, Chhattisgarh, India3 yrs 11 mos experience
Highly Stable

Key Highlights

  • Expert in Universal Verification Methodology and SystemVerilog.
  • Experience in low power management for 5G modem technology.
  • Strong background in digital circuit and integrated circuit design.
Stackforce AI infers this person is a Telecommunications and Semiconductor professional with expertise in design verification and software development.

Contact

Skills

Core Skills

Universal Verification Methodology (uvm)SystemverilogC++Digital Signal Processing

Other Skills

C (Programming Language)Cadence VirtuosoVerilogDigital Circuit DesignIntegrated Circuit DesignMATLABCadence Virtuoso Layout EditorRF CircuitsSPICEAVR-CData StructuresShell ScriptingSPICE Coding

Experience

3 yrs 11 mos
Total Experience
3 yrs 11 mos
Average Tenure
3 yrs 11 mos
Current Experience

Qualcomm

2 roles

Senior Design Verification Engineer

Promoted

Dec 2024Present · 1 yr 6 mos

Universal Verification Methodology (UVM)SystemVerilogC (Programming Language)Cadence VirtuosoVerilogDigital Circuit Design+1

Design Verification Engineer

Jul 2022Dec 2024 · 2 yrs 5 mos

  • Working on IPA(Internet Protocol Accelerator)
Universal Verification Methodology (UVM)SystemVerilogC (Programming Language)Digital Circuit Design

Apple

Software Development Engineering Intern

Jan 2022Jun 2022 · 5 mos · Bengaluru, Karnataka, India

  • Worked on Modem Power Driver Software, responsible for low power management on 5G modem.
C++MATLABDigital Signal Processing

Education

Indian Institute Of Information Technology Allahabad

B. Tech + M. Tech

Jan 2017Jan 2022

Jawahar Navodaya Vidyalaya - JNV

Higher Secondary School Certificate — PCM

Jan 2015Jan 2016

Jawahar Navodaya Vidyalaya - JNV

Secondary School Certificate

Jan 2013Jan 2014

Stackforce found 100+ more professionals with Universal Verification Methodology (uvm) & Systemverilog

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