Jan 2023 – Dec 2025 · 2 yrs 11 mos · Bengaluru, Karnataka, India · Hybrid

• √ Worked in the Clock Gating low power synthesis and SOC power Computation/Analysis/Optimization EDA software tools research & development (R&D) team/organization that are the implementation/synthesis/power computation software tools called Innovus/Genus/Joules of the company

Jul 2018 – Dec 2022 · 4 yrs 5 mos · Bengaluru, Karnataka, India

• √ Developed, maintained, and debugged various customer issues and enhancement requests of silicon/hardware design for testability (DFT)/Fusion compiler (FC) EDA tool while working as a backend developer in their TDM/NDM team, which is basically the test/new data model team working on designing, enhancing, maintaining, and debugging backend data model flow/structure for the IC Compiler EDA Tool
• √ Developed, maintained, and debugged various customer issues and enhancement requests of the backend data model of the IP/Core Tools, which consist of mainly three different flavours of the top-level tool named coreConsultant, coreBulder, and coreAssembler which are used primarily to validate the subsystems of the designs by running synthesis, simulation, formal verification, and timing analysis
• √ Worked in the Clock Tree Synthesis/Optimization R&D team of ICC EDA Software Tool, a digital place & route infra/platform of the company

Jun 2014 – Jun 2018 · 4 yrs · Bengaluru, Karnataka, India

• √ Developed, maintained, and debugged various customer issues and enhancement requests of the backend data model of ICV EDA software tool which is used primarily to validate the DRC/LVS runsets and predict the correctness of the schematic vs. layout representations of the ASIC digital designs
• √ Developed, maintained, and debugged various regressions infrastructure utilities and the issues single handily for all the IP/Core EDA software tools of the company to automate their end usage and overall performance analysis upfront