Ayush Maheshwari

Software Engineer

Jaipur, Rajasthan, India5 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in Formal Verification and SystemVerilog.
Proven track record in semiconductor project implementations.
Strong leadership experience in academic placement coordination.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in verification and project management.

Contact

Skills

Core Skills

Formal VerificationSystemverilogC++

Other Skills

JenkinsUVMData StructuresProject ManagementMachine LearningVerilogCMatlabMicrosoft OfficeLeadershipManagementTeam LeadershipTeam ManagementGNU octaveLabcenter Proteus

About

Exploring tech !!

Experience

5 yrs 11 mos

Total Experience

2 yrs 1 mo

Average Tenure

1 yr 8 mos

Current Experience

Amd

Senior Silicon Design Engineer

Oct 2024 – Present · 1 yr 8 mos · India · On-site

Analog devices

2 roles

Design Verification Engineer

Promoted

Apr 2023 – Oct 2024 · 1 yr 6 mos

Associate Engineer

Jun 2021 – Apr 2023 · 1 yr 10 mos

National institute of technology,kurukshetra

2 roles

Placement Coordinator

Jul 2020 – Jun 2021 · 11 mos

I am Placement Coordinator at Training and Placement Cell, NIT Kurukshetra. I am looking and coordinating with all the Placement related processes within campus.

Internship Coordinator

Feb 2019 – Jul 2020 · 1 yr 5 mos

I was the Internship Coordinator at Training and Placement Cell, NIT Kurukshetra. I looked over and coordinated with all the Internship related processes within campus.

Samsung electronics

Assistant Engineer

Jan 2020 – Jul 2020 · 6 mos · bangalore

Part of the team working on implementing DDR5 Behavioral Model (BM) and was able to complete formal verification of some sub-modules of DDR5.
Worked on implementation of BCH Error Correction Code (ECC) and was able to present a complete C++ model for that which included completed Encoding and Decoding.
Developed an asynchronous First in First Out (FIFO) device in System Verilog and wrote assertions for the same for its functional verification and verified it by creating a test-bench.

C++SystemVerilogFormal Verification