Balasubrahmanyam M

Director of Engineering

Bengaluru, Karnataka, India24 yrs 3 mos experience
Highly Stable

Key Highlights

  • 20 years of experience in semiconductor development.
  • Led teams delivering solutions for 15+ CPU platforms.
  • Pioneered Virtual prototype development for pre-silicon verification.
Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in pre-silicon and post-silicon validation.

Contact

Skills

Core Skills

System DebugFirmware IntegrationVirtual PrototypesPost Silicon Validation

Other Skills

ValidationPre-Silicon VerificationMobile Baseband SoCEmbedded SystemsARMASICEmbedded SoftwareSemiconductorsSoCDevice Drivers

About

I am an Intel Director of Engineering and have been working at Intel India for past 20 years and worked in several areas of semiconductor development life cycle, including RTL design, IP verification, Simulation/Emulation development (Virtual Prototypes), Post Silicon validation, Pre and Post silicon FW/SW/System validation, System Bring up (Power on) and System Debug. most recently I have been leading the System Debug and firmware integration and Validation efforts for Intel Network and Edge Computing Business group. I have successfully 1. Led System Debug and FW integration team and delivered System bring up, System Debug support for 15+ CPU platforms for Edge computing business. 2. Led Virtual prototype and Pre-Si verification strategy and delivered full system simulation platforms (Virtual prototype) for 20+ Mobile baseband SoCs for Intel Communication Devices group 3. Led Post Silicon validation efforts for Mobile baseband SoCs and successfully brought up 12+ SoC platforms Over the course of my career at Intel I have pioneered Virtual prototype development and usage for pre-si FW/SW verification, Simulation architecture and built and managed several technical teams across multiple Geo locations and led four functional organisations (Post silicon validation, Virtual prototypes, System Debug, FW integration and Validation)

Experience

24 yrs 3 mos
Total Experience
4 yrs 1 mo
Average Tenure
1 yr 2 mos
Current Experience

Amd

Sr Manager Silicon Design Engineering

Mar 2025Present · 1 yr 2 mos

Intel corporation

2 roles

Director of Engineering - System Debug, System Modeling

Promoted

Sep 2018Nov 2024 · 6 yrs 2 mos

  • Leading System Debug and Firmware Integration & Validation activities for Intel Network and Edge products, bridging the gap between SW Validation, Development, Platform Application Engineering, and Product Management teams.
  • Head of the Virtual Prototype organization for Intel Modem SoC products, responsible for functional management, architecture, and design of the Virtual prototype solutions. Successfully delivered pre-silicon platform solutions to internal and external customers for over 8 generations of Intel products.
System DebugFirmware IntegrationValidationVirtual PrototypesPre-Silicon Verification

Technical Architect & Senior Manager - Virtual Prototype Systems [Modem SoCs]

Apr 2015Aug 2018 · 3 yrs 4 mos

Intel mobile communications pvt ltd

Manager

Apr 2009Apr 2015 · 6 yrs · Bangalore

  • Responsible for delivering Virtual prototype system for Intel modem platforms enabling pre-silicon verification of SW/FW and reducing the product development times
Virtual PrototypesPre-Silicon Verification

Infineon technologies

Senior Design Engineer

Oct 2007Sep 2010 · 2 yrs 11 mos · Bangalore

  • Responsible for design, development of Virtual Prototype solutions for Infineon's Mobile baseband SoC, Influenced SW/FW leadership by demonstrating SW shift left capabilities of Virtual Prototype platforms and accelerated the usage Virtual prototype platforms for Pre-Si SW/FW development and validation,
Virtual PrototypesMobile Baseband SoC

Agere systems

Tech Lead

Feb 2005Oct 2007 · 2 yrs 8 mos

  • Responsible for post silicon validation of 2nd and 3rd Generation mobile baseband SoCs and introduced and developed Virtual prototype platforms for early silicon validation test suit development
Post Silicon ValidationVirtual Prototypes

St microelectronics

software engineer

Jan 2004Jan 2005 · 1 yr · Noida Area, India

  • Developed board-level functional verification environments for form factor boards during assembly line, including memory and IO test suites. Also served as a single point of contact for HW management and maintenance at ST Noida.

Bharat electronics

Member Research Staff

Jul 2001Dec 2003 · 2 yrs 5 mos

  • Led the development of CPCI formfactor Motherboard as a technology demonstration for Indian Navy main computer systems, Responsible for HW design, schematics entry, PCB design and board bring up to OS boot.

Education

Birla Institute of Technology and Science, Pilani

ME — Electronics & Control

Jan 2000Jan 2001

N.B.K.R.Institute of Science & Technology (affiliated to S.V University)

Bachelor of Technology (B.Tech.) — Electrical and Electronics Engineering

Jan 1994Jan 1998

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