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Dharmendar Reddy Palle

Machine Learning Engineer

Seattle, Washington, United States12 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 15+ years in high-performance parallel coding
  • Expertise in AI and deep learning frameworks
  • Strong background in semiconductor device physics
Stackforce AI infers this person is a Semiconductor and Machine Learning expert with extensive experience in high-performance computing.

Contact

Skills

Core Skills

Machine LearningDeep LearningSemiconductor TechnologyDevice Simulation

Other Skills

C++PythonLinuxDevice TechnologyTCADSilicon ModelingBenchmarkingGraphene Transistor ModelingCircuit AnalysisManagementProduct ManagementNanotechnologyResearchMatlabSimulations

About

I have 15+ years experience in developing high performance parallel codes in C++/Fortran. Deployed codes in large distributed systems and resource constrained edge devices. Working experience of numerical packages (such as PETSc, Trillionos, Intel MKL etc), Deep learning frameworks (PyTorch, TensorFlow) and inference runtimes (onnxruntime and OpenVINO). Experience in deploying codes to Jetson Nano echo system, Intel VPU chips. 1. Tech lead for implementation AI-powered active speaker detection and multiple video stream generation for Intelligent camera for Teams (https://bit.ly/3JxKkj2) 2. Experienced in End-to-End Machine learning flow with audio/visual data. 3. Model optimization and deployment for realtime audio/video inference in resource constrained devices. Additionally, I also have strong back ground in Semiconductor device physics and Technology. 1. Over 6 year of experience in leading semiconductor device technology path finding for 7nm, 5nm, 3nm and beyond nodes. 2. Performed TCAD and first principles analysis of Semiconductor devices (FinFET, MBCFET etc) with commercial and in-house tools. 3. Extensively worked in HPC cluster environment with large parallel codes such as NEMO. 4. Skilled in Device simulation, Circuit simulation, Classical and Quantum electron transport, Research Management etc. Technical Skills: • Device/Circuit Simulators: Cadence Spectre, HSPICE, Synopsys TCAD (device/process) simulation tools • Mathematical Tools: MATLAB/Octave, Mathematica, R, numerical libraries (PETSc, Trillinos, MKL etc) • Core Programming: C++/C/C#, Python, FORTRAN, MPI/OpenMP, TCL, Scheme • Data Science/ML: Pytorch, caffe/caffe2, Tensorflow, scikit-learn ,SQL • Web/App development: HTML5, CSS3, JavaScript, familiarity with AngularJS/ReactJS, .Net UWP • Development Tools: Linux scripting/build tools, version control (git, svn etc), debug/profiling, LSF/UGE/SLURM

Experience

12 yrs 10 mos
Total Experience
4 yrs 3 mos
Average Tenure
5 yrs 5 mos
Current Experience

Microsoft

Senior Machine Learning Engineer

Jan 2021Present · 5 yrs 5 mos

Machine LearningDeep LearningC++PythonLinux

Samsung electronics

3 roles

Sr. Staff Research Engineer

Promoted

Mar 2019Mar 2020 · 1 yr

  • 1. Performed Device Technology path finding for 10nm, 7nm, 5nm, 3nm and beyond nodes
  • 2. Led Device TCAD research work for Finfet and MBCFET (Nano sheet) for beyond 7nm node applications
  • 3. Developed TCAD and Compact models for Silicon, SiGe and III-V based devices for Device Technology Co-optimization (DTCO)
  • 4. Experienced in technology benchmarking with cell/ring oscillator level simulations
  • 5. Evaluated various CMOS and beyond CMOS devices (eg: tunnel FETs ) for insertion in beyond 7nm nodes
  • 6. Performed research on device options for deep learning accelerators (xBar architecture for matrix vector multiplication)
Device TechnologyTCADSilicon ModelingBenchmarkingSemiconductor TechnologyDevice Simulation

Staff Research Engineer

Mar 2017Feb 2019 · 1 yr 11 mos

Sr. Research Scientist

Jun 2013Feb 2017 · 3 yrs 8 mos

Ibm

3 roles

Device Research Intern

Jun 2011Dec 2011 · 6 mos · Austin, Texas Area

  • As an Intern at IBM Research labs at Austin, I developed a hardware correlated compact model for long
  • channel graphene field effect transistor. I used the model to analyze the performance of a radio frequency mixer and a low noise amplifier circuit. In addition, we used the simple device model to explain effect of thin gate dielectrics in enabling current saturation in sub-micrometer graphene transistors
Graphene Transistor ModelingCircuit AnalysisDevice Simulation

Device Research Intern

Jan 2011May 2011 · 4 mos · Austin, Texas Area

Device Research Intern

Jun 2010Dec 2010 · 6 mos · Austin, Texas Area

Education

The University of Texas at Austin

Doctor of Philosophy (Ph.D.) — Solid State Electronics

Jan 2006Jan 2013

The University of Texas at Austin

Master of Science in Engineering- MSE — Electrical and Computer Engineering

Jan 2006Jan 2008

Indian Institute of Technology, Kanpur

Bachelor’s Degree — Electrical Engineering

Jan 2002Jan 2006

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